From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Jisheng Zhang <jszhang@kernel.org>,
Yunhui Cui <cuiyunhui@bytedance.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v6 05/13] riscv: Only send remote fences when some other CPU is online
Date: Tue, 26 Mar 2024 21:49:46 -0700 [thread overview]
Message-ID: <20240327045035.368512-6-samuel.holland@sifive.com> (raw)
In-Reply-To: <20240327045035.368512-1-samuel.holland@sifive.com>
If no other CPU is online, a local cache or TLB flush is sufficient.
These checks can be constant-folded when SMP is disabled.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v4)
Changes in v4:
- New patch for v4
arch/riscv/mm/cacheflush.c | 4 +++-
arch/riscv/mm/tlbflush.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index d76fc73e594b..f5be1fec8191 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -21,7 +21,9 @@ void flush_icache_all(void)
{
local_flush_icache_all();
- if (riscv_use_sbi_for_rfence())
+ if (num_online_cpus() < 2)
+ return;
+ else if (riscv_use_sbi_for_rfence())
sbi_remote_fence_i(NULL);
else
on_each_cpu(ipi_remote_fence_i, NULL, 1);
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index da821315d43e..0901aa47b58f 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -79,7 +79,9 @@ static void __ipi_flush_tlb_all(void *info)
void flush_tlb_all(void)
{
- if (riscv_use_sbi_for_rfence())
+ if (num_online_cpus() < 2)
+ local_flush_tlb_all();
+ else if (riscv_use_sbi_for_rfence())
sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, FLUSH_TLB_NO_ASID);
else
on_each_cpu(__ipi_flush_tlb_all, NULL, 1);
--
2.43.1
next prev parent reply other threads:[~2024-03-27 4:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-27 4:49 [PATCH v6 00/13] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-03-27 4:49 ` [PATCH v6 01/13] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-04-24 20:50 ` Alexandre Ghiti
2024-03-27 4:49 ` [PATCH v6 02/13] riscv: Factor out page table TLB synchronization Samuel Holland
2024-04-04 7:48 ` Alexandre Ghiti
2024-03-27 4:49 ` [PATCH v6 03/13] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-04-04 7:56 ` Alexandre Ghiti
2024-03-27 4:49 ` [PATCH v6 04/13] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-03-27 4:49 ` Samuel Holland [this message]
2024-03-27 6:16 ` [External] [PATCH v6 05/13] riscv: Only send remote fences when some other CPU is online yunhui cui
2024-03-27 20:14 ` Samuel Holland
2024-03-28 2:21 ` yunhui cui
2024-04-04 8:04 ` Alexandre Ghiti
2024-03-27 4:49 ` [PATCH v6 06/13] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-03-27 6:23 ` [External] " yunhui cui
2024-03-27 4:49 ` [PATCH v6 07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-03-27 4:49 ` [PATCH v6 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-03-27 6:27 ` [External] " yunhui cui
2024-03-27 4:49 ` [PATCH v6 09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-03-27 4:49 ` [PATCH v6 10/13] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-03-27 4:49 ` [PATCH v6 11/13] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-03-27 4:49 ` [PATCH v6 12/13] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-03-27 4:49 ` [PATCH v6 13/13] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-05-14 14:00 ` [PATCH v6 00/13] riscv: ASID-related and UP-related TLB flush enhancements patchwork-bot+linux-riscv
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