From: Aravinda Prasad <aravinda.prasad@intel.com>
To: damon@lists.linux.dev, linux-mm@kvack.org, sj@kernel.org,
linux-kernel@vger.kernel.org
Cc: aravinda.prasad@intel.com, s2322819@ed.ac.uk,
sandeep4.kumar@intel.com, ying.huang@intel.com,
dave.hansen@intel.com, dan.j.williams@intel.com,
sreenivas.subramoney@intel.com, antti.kervinen@intel.com,
alexander.kanevskiy@intel.com
Subject: [PATCH v2 3/3] mm/damon: documentation updates
Date: Mon, 18 Mar 2024 18:58:48 +0530 [thread overview]
Message-ID: <20240318132848.82686-4-aravinda.prasad@intel.com> (raw)
In-Reply-To: <20240318132848.82686-1-aravinda.prasad@intel.com>
This patch updates the kernel documentation.
Signed-off-by: Aravinda Prasad <aravinda.prasad@intel.com>
---
Documentation/mm/damon/design.rst | 42 +++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/mm/damon/design.rst b/Documentation/mm/damon/design.rst
index 5620aab9b385..59014ecbb551 100644
--- a/Documentation/mm/damon/design.rst
+++ b/Documentation/mm/damon/design.rst
@@ -139,6 +139,48 @@ the interference is the responsibility of sysadmins. However, it solves the
conflict with the reclaim logic using ``PG_idle`` and ``PG_young`` page flags,
as Idle page tracking does.
+Profiling enhancement for virtual address space
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For virtual address space tracking, relying on checking Accessed bit(s) only
+at the leaf level of the page table is inefficient. Hardware architectures
+have supported Accessed bit(s) at all levels of the page table tree by
+updating them during the page table walk. Hence, DAMON dynamically
+profiles different levels (PMD/PUD/P4D) of a multi-level page table tree.
+
+DAMON leverages the following key insight: a data page that is accessed
+should also have the Accessed bit set at PMD, PUD, P4D, and PGD entry.
+Similarly, if the Accessed bit in a PGD entry (or a PUD/PMD entry) is
+not set, then none of the data pages under the PGD entry (or PUD/PMD
+entry) subtree are accessed. DAMON profiles Accessed bits at the highest
+possible level of the page table tree to identify the regions that are
+accessed.
+
+For example, consider a region and the sampling address (SA) in the below
+figure. The address range of a PUD entry corresponding to SA is within
+region bounds and hence PUD is picked for checking and setting the
+Accessed bits. However, this not true if P4D is picked for profiling.
+Hence in this case PUD is the highest possible level that can be picked
+for profiling.
+ .......
+ + P4D +
+ .......
+ / \
+ / \
+ / \
+ / \
+ / \
+ / ....... \
+ / + PUD + \
+ / ....... \
+ / / \ \
+- - - - - +-----*---*--+====+-*------+- -*- - -
+ + # SA # +
+ + # # +
+- - - - - +------------+====+--------+- - - - -
+
+ | ----- DAMON region ------|
+
Core Logics
===========
--
2.21.3
next prev parent reply other threads:[~2024-03-18 13:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-18 13:28 [PATCH v2 0/3] mm/damon: Profiling enhancements for DAMON Aravinda Prasad
2024-03-18 13:28 ` [PATCH v2 1/3] mm/damon: mm infrastructure support Aravinda Prasad
2024-03-18 20:27 ` kernel test robot
2024-03-18 13:28 ` [PATCH v2 2/3] mm/damon: profiling enhancement Aravinda Prasad
2024-03-18 18:23 ` kernel test robot
2024-03-18 21:59 ` kernel test robot
2024-03-18 13:28 ` Aravinda Prasad [this message]
2024-03-19 0:51 ` [PATCH v2 0/3] mm/damon: Profiling enhancements for DAMON Yu Zhao
2024-03-19 5:20 ` SeongJae Park
2024-03-19 10:56 ` Prasad, Aravinda
2024-03-20 12:31 ` Prasad, Aravinda
2024-03-21 23:10 ` SeongJae Park
2024-03-22 12:12 ` Prasad, Aravinda
2024-03-22 18:32 ` SeongJae Park
2024-03-25 7:50 ` Prasad, Aravinda
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