From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C133C48BC4 for ; Tue, 20 Feb 2024 12:21:23 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 126B36B0072; Tue, 20 Feb 2024 07:21:23 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 0D80E6B0075; Tue, 20 Feb 2024 07:21:23 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id F08188D0001; Tue, 20 Feb 2024 07:21:22 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id E1BCC6B0072 for ; Tue, 20 Feb 2024 07:21:22 -0500 (EST) Received: from smtpin13.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 7EF92140685 for ; Tue, 20 Feb 2024 12:21:22 +0000 (UTC) X-FDA: 81812092404.13.F553E9D Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by imf30.hostedemail.com (Postfix) with ESMTP id 28B4F8001E for ; Tue, 20 Feb 2024 12:21:19 +0000 (UTC) Authentication-Results: imf30.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=cziAa188; spf=pass (imf30.hostedemail.com: domain of will@kernel.org designates 145.40.73.55 as permitted sender) smtp.mailfrom=will@kernel.org; dmarc=pass (policy=none) header.from=kernel.org ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1708431680; a=rsa-sha256; cv=none; b=e1JYi/UlB/9jWD336Uq7T3wvHQnaoganVany2CZs1DYrrO//7Op5+GiQdZy/SGHcPL6k8n 55XJZt7JgkQAd92AxX7MlnkpwFlyPdl/silGW8Nb0pRS9dsUEyb8EQQ7DmCvsPTUwZoZkJ xmpok/5+uOYuAYJAc4UtUtMWHNHEsvA= ARC-Authentication-Results: i=1; imf30.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=cziAa188; spf=pass (imf30.hostedemail.com: domain of will@kernel.org designates 145.40.73.55 as permitted sender) smtp.mailfrom=will@kernel.org; dmarc=pass (policy=none) header.from=kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1708431680; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=24uLHaCjaD7I0U2+Mvga1EGarJuqLzJR+x+7J8wB8Ns=; b=q42oPx2QY1Q/SoQ54F3jSKWFkcp4PeQFWd6enqBxrD0pB9dskHzf2Rma2saT3JB+yGGb1i 1aB7S9INERbcEUXt0z6lTVw/Ad7q/NC0dgz+G9KZgKBLXrjeL1X/okKRmsBNjz5wMohabL gZMCgjxkWhegUnbQG0+f28Zv0XihGvI= Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 466C0CE1264; Tue, 20 Feb 2024 12:21:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C71BBC433F1; Tue, 20 Feb 2024 12:21:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708431674; bh=jV03GKfaPISem9za3Whs0Xc2NpK5afZ4kewZC3epk98=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=cziAa1884tUKYj/oG8oWpobatz95huFTEsocTtFryUfPMNk0dBnW99+7ceeiv4P81 +QfVIcLde0P6FkNqbuBOcErf/6T5q72XSK6OkM7mn8kplaWIaahuAyZLqn4Pi1VoJd u44VIuTCDHNbvLp6vkkYWALYzYxiOJcqqyE0FoMvv8ZFP8A03EprTOhgHVouyNbZij s61RWM4gGhaLBzTkLPAK2YkwOB625VirQDb714AkZHhF854/7dos9AEyO+qPP6PgkZ 71emIScEs6bYH9ezmMYm15fYahRwgf3iVV/DfI66Y0bHAPOebWTndru4ZXZZjmfzMG anrc9g+6GnRRQ== Date: Tue, 20 Feb 2024 12:21:03 +0000 From: Will Deacon To: ankita@nvidia.com Cc: jgg@nvidia.com, maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, reinette.chatre@intel.com, surenb@google.com, stefanha@redhat.com, brauner@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, alex.williamson@redhat.com, kevin.tian@intel.com, yi.l.liu@intel.com, ardb@kernel.org, akpm@linux-foundation.org, andreyknvl@gmail.com, wangjinchao@xfusion.com, gshan@redhat.com, shahuang@redhat.com, ricarkol@google.com, linux-mm@kvack.org, lpieralisi@kernel.org, rananta@google.com, ryan.roberts@arm.com, david@redhat.com, linus.walleij@linaro.org, bhe@redhat.com, aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, kvmarm@lists.linux.dev, mochs@nvidia.com, zhiw@nvidia.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 1/4] kvm: arm64: introduce new flag for non-cacheable IO memory Message-ID: <20240220122103.GB5613@willie-the-truck> References: <20240220072926.6466-1-ankita@nvidia.com> <20240220072926.6466-2-ankita@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240220072926.6466-2-ankita@nvidia.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: 28B4F8001E X-Stat-Signature: sp41grgd417zahfs7jmozzow6o7s6k1r X-Rspam-User: X-HE-Tag: 1708431679-68063 X-HE-Meta: U2FsdGVkX185JUCcOQ2nQrnkCTh0uZG/d0M4lqMU3V+xPuM7E9TTKNKXUdIh5ghv7mAPVKmmhcD2LvHmyN0K86BDukgfK9i6gyV8cg2Kn+1nk9cQhnYMCQA7k3TXh8tuG6C2MX8z3FdjbUbwwST6es5EUx8AQL8fOD8BetXJ4uxCLlkqMHKfuZ04+kY8iPmeYzZ9hExcziPcudqcCdqfGo0UalEf4oBoK4gl1UiDphzp5KLx9RVwxAH7tI4nqPkPKk+tsJUUG4L0J/pMyPHlO7t6t0nOVMS2x+HkogmJL+e2uCSGIOi55m7TZQuMkI7TQnNefc3V5X/kIEgigaUacXV5ImAFuWJIhx78B8Blmo9IrKprDkRgAbWudhZQXVUFeh8oG66FZSARuoVuGS12o+MyZljBUxB2kyQ1uzyZFEAN3YVh8zNSey/CYaRPiBHYzqJUc5xdvi/rapVF9jMV71NHPSpjIU9DD8IXQ15HH0/PrrVkVKZ6j/wgJzA15Xa/72aPDZcgsgbXTLZTrbYvg2DbjPMK9TtgMpckY0dEkMq0IN6EhegzlDR+nttgGeEE3fpPVDcqNPyUPsnONzOaUbzfQaNsHIFc416hNlD98imYZ2hlNMNYzVFpS5ygzWS/Q5/n99SoSMNLGSSYxvQreddkZPMUDupTbfqXWWrA665p3zkkZVnUzQGpIZOmgMXNhFLK8cYTAq36YEB2oEL+deSTqTVd2jnZzBkKO+MvPqpm7uu0cf6kqMM7gow9IcyG62nnIBVS92t0Tj9DhaGb4/B/H+BhK8vBHhjimk/OLyvw4KVMm9MT3Nk6mLjP27IwRUtSlCst/g0zPPo4cj4vYogsOmlCWvgc9uL+AptXiQ43govMNyBRQi9Umm5X2ipbA7keLW5ZnCv7cwflM1FUFLa9/OBeEP68wy6TSCW+5JQrCjaTmXg9tkLVJKYxfWeFheB0ZZ3KdWsjtH7iNrF mVjf5sK7 SdlwhokZSL0fmHQvjdQSv47yAD/aMBrPXfuyJ8avWN6dW3gsI08QcPDAI5myXixuF77jfAGOK7AqzykxsmMHKaNKWjyN5WoS6aqc+lHvCjMNKS3Nto6664OUmD4Rx/hnnXImhv8+rX5Zf06gYy8+C7+3SvtW7Y7MonDmCjuK8BmDC1rz9ZOqIsgzSpuUzbwjV8bcz+br84+v9SxQx5yiGKGbUvcvJP0o73rQlzWqQ3xCple/0QiZLTPMeQ7T376z3RPtWC7WNLxN4g20OmvSAFrCOgHmABtCHnBt1KevgZjhgWnXYmxQ3E9yPMsHHOmvExpQvoY7yefwKgiw= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Feb 20, 2024 at 12:59:23PM +0530, ankita@nvidia.com wrote: > From: Ankit Agrawal > > Currently, KVM for ARM64 maps at stage 2 memory that is considered device > (i.e. it is not RAM) with DEVICE_nGnRE memory attributes; this setting > overrides (as per the ARM architecture [1]) any device MMIO mapping > present at stage 1, resulting in a set-up whereby a guest operating > system cannot determine device MMIO mapping memory attributes on its > own but it is always overridden by the KVM stage 2 default. > > This set-up does not allow guest operating systems to select device > memory attributes independently from KVM stage-2 mappings > (refer to [1], "Combining stage 1 and stage 2 memory type attributes"), > which turns out to be an issue in that guest operating systems > (e.g. Linux) may request to map devices MMIO regions with memory > attributes that guarantee better performance (e.g. gathering > attribute - that for some devices can generate larger PCIe memory > writes TLPs) and specific operations (e.g. unaligned transactions) > such as the NormalNC memory type. > > The default device stage 2 mapping was chosen in KVM for ARM64 since > it was considered safer (i.e. it would not allow guests to trigger > uncontained failures ultimately crashing the machine) but this > turned out to be asynchronous (SError) defeating the purpose. > > Failures containability is a property of the platform and is independent > from the memory type used for MMIO device memory mappings. > > Actually, DEVICE_nGnRE memory type is even more problematic than > Normal-NC memory type in terms of faults containability in that e.g. > aborts triggered on DEVICE_nGnRE loads cannot be made, architecturally, > synchronous (i.e. that would imply that the processor should issue at > most 1 load transaction at a time - it cannot pipeline them - otherwise > the synchronous abort semantics would break the no-speculation attribute > attached to DEVICE_XXX memory). > > This means that regardless of the combined stage1+stage2 mappings a > platform is safe if and only if device transactions cannot trigger > uncontained failures and that in turn relies on platform capabilities > and the device type being assigned (i.e. PCIe AER/DPC error containment > and RAS architecture[3]); therefore the default KVM device stage 2 > memory attributes play no role in making device assignment safer > for a given platform (if the platform design adheres to design > guidelines outlined in [3]) and therefore can be relaxed. > > For all these reasons, relax the KVM stage 2 device memory attributes > from DEVICE_nGnRE to Normal-NC. > > The NormalNC was chosen over a different Normal memory type default > at stage-2 (e.g. Normal Write-through) to avoid cache allocation/snooping. > > Relaxing S2 KVM device MMIO mappings to Normal-NC is not expected to > trigger any issue on guest device reclaim use cases either (i.e. device > MMIO unmap followed by a device reset) at least for PCIe devices, in that > in PCIe a device reset is architected and carried out through PCI config > space transactions that are naturally ordered with respect to MMIO > transactions according to the PCI ordering rules. > > Having Normal-NC S2 default puts guests in control (thanks to > stage1+stage2 combined memory attributes rules [1]) of device MMIO > regions memory mappings, according to the rules described in [1] > and summarized here ([(S1) - stage1], [(S2) - stage 2]): > > S1 | S2 | Result > NORMAL-WB | NORMAL-NC | NORMAL-NC > NORMAL-WT | NORMAL-NC | NORMAL-NC > NORMAL-NC | NORMAL-NC | NORMAL-NC > DEVICE | NORMAL-NC | DEVICE > > It is worth noting that currently, to map devices MMIO space to user > space in a device pass-through use case the VFIO framework applies memory > attributes derived from pgprot_noncached() settings applied to VMAs, which > result in device-nGnRnE memory attributes for the stage-1 VMM mappings. > > This means that a userspace mapping for device MMIO space carried > out with the current VFIO framework and a guest OS mapping for the same > MMIO space may result in a mismatched alias as described in [2]. > > Defaulting KVM device stage-2 mappings to Normal-NC attributes does not > change anything in this respect, in that the mismatched aliases would > only affect (refer to [2] for a detailed explanation) ordering between > the userspace and GuestOS mappings resulting stream of transactions > (i.e. it does not cause loss of property for either stream of > transactions on its own), which is harmless given that the userspace > and GuestOS access to the device is carried out through independent > transactions streams. > > A Normal-NC flag is not present today. So add a new kvm_pgtable_prot > (KVM_PGTABLE_PROT_NORMAL_NC) flag for it, along with its > corresponding PTE value 0x5 (0b101) determined from [1]. > > Lastly, adapt the stage2 PTE property setter function > (stage2_set_prot_attr) to handle the NormalNC attribute. > > [1] section D8.5.5 - DDI0487J_a_a-profile_architecture_reference_manual.pdf > [2] section B2.8 - DDI0487J_a_a-profile_architecture_reference_manual.pdf > [3] sections 1.7.7.3/1.8.5.2/appendix C - DEN0029H_SBSA_7.1.pdf > > Suggested-by: Jason Gunthorpe > Acked-by: Catalin Marinas > Signed-off-by: Ankit Agrawal > --- > arch/arm64/include/asm/kvm_pgtable.h | 2 ++ > arch/arm64/include/asm/memory.h | 2 ++ > arch/arm64/kvm/hyp/pgtable.c | 24 +++++++++++++++++++----- > 3 files changed, 23 insertions(+), 5 deletions(-) Acked-by: Will Deacon Will