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Thu, 4 Jan 2024 14:42:08 +0000 (UTC) Date: Thu, 4 Jan 2024 15:42:02 +0100 From: Borislav Petkov To: Michael Roth Cc: x86@kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, jroedel@suse.de, thomas.lendacky@amd.com, hpa@zytor.com, ardb@kernel.org, pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, jmattson@google.com, luto@kernel.org, dave.hansen@linux.intel.com, slp@redhat.com, pgonda@google.com, peterz@infradead.org, srinivas.pandruvada@linux.intel.com, rientjes@google.com, tobin@ibm.com, vbabka@suse.cz, kirill@shutemov.name, ak@linux.intel.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, alpergun@google.com, jarkko@kernel.org, ashish.kalra@amd.com, nikunj.dadhania@amd.com, pankaj.gupta@amd.com, liam.merwick@oracle.com, zhi.a.wang@intel.com, Brijesh Singh Subject: Re: [PATCH v1 04/26] x86/sev: Add the host SEV-SNP initialization support Message-ID: <20240104144202.GGZZbDuutFUFmktT7M@fat_crate.local> References: <20231230161954.569267-1-michael.roth@amd.com> <20231230161954.569267-5-michael.roth@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231230161954.569267-5-michael.roth@amd.com> X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: BD3B540029 X-Stat-Signature: kbheuexrhh31sgqpe7jqtekaskwa9ird X-HE-Tag: 1704379373-600732 X-HE-Meta: U2FsdGVkX19vjmfk2uEltQVRTm1/KlLOPDrxQlDXXDAoPSoiqADOYR6PYgik0B1o3tgG4vIEOpFMETBazA7fymS1T02Dl/SgPRtZRmv8APv88iShbIyEf73nQyP0a5gfcODLdK4pdCNP6dkhZtdNqkE8w4b0G+ZxuYaNzKQXZER7ChEFyGavxoONTQ/1f1g8KeVY9K85NXkq21IW7hLjryen9l2M7gu/bQnbDVZfxPVyK2/F5rPVLK3RpPJhWI5qGNmzJQeNz0SDQ8Nv65ssvYEctZfR5Svphcvvp9Jus6T0989tgATTpas5O519IKBpu/xTGKUpLxyVrqclwYoRvWNoJZRQcmPqi/8PixQql7lthDByWzQvyGLtWA9LHR4hPsmO1+o9JZhvRQUoaCxkmdeJKhYDZaZMZ8LIMqoiTDEyRhzopnOgkdwf3XrO0GeFph945IdZvnfOWi+Z8UnZPrGt0jurR/wMNHDgIOP3VAYD3X8zfKGL4JtzU5HJadRQ+wuWuepByXLWfZ2AymJN3XmarnMiSxKxPbZBeJ6vfPyHoSO4D+jRge72UTSj0K1uUhJh/Hee6Ptu2k/JP540yiqVOeq4MRWPr/8X/72/4Q0Z61c+IeJ3NjE3eTWMxlAnSCeDtgNqdUqivx4SHcOczamr15IWj0slhfl108qRZcyH4xJJD2FMEfTezQJe+MTq+4TeYihB/YLJfUdWBuZjbmQN+q+NaZz9qJuZEG/MZLwPBNKy8vIJJHpGely2yrr7LtiWVutCnh5KNtnVm0qB/uZBi54fuF+hpYWxkRT87gtrU0f6+YQGgDqmMcliocMEeaNbMg1rfuwFssFJsMGGCGbIGp6J4fUcz8GfAh/eF1MQ+q9Wf5wmb23s5Zs94EDfBipf4Vi1ByrxgyAU01+025fOXotJZUNEzpxnPBFJ4Egu1lSdl2ceyNsFRo22gY8CeZAMxNx2mNnPic7Qp4Y LaXbHA9V rwqt9sXGcFoXLHag2kYDLhjeRT1njrL6X64MDUKicqf+nNuyJ2PFMFgCAYBnK58ImWTmTZlRXgjXi07xj/BY6iB8bxX4Izg+x3REL0FpGxcRZfd5XKiLMK+38P/Kb7nMdauIgJW3RT/3tSA+/SRlerv39sCCXPvszV0j6WmIN9bidtnZZ0il5YM8NL2kCqeGDauVj/9jjxnnSO0E= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Sat, Dec 30, 2023 at 10:19:32AM -0600, Michael Roth wrote: > + if (cpu_has(c, X86_FEATURE_SEV_SNP)) { > + /* > + * RMP table entry format is not architectural and it can vary by processor > + * and is defined by the per-processor PPR. Restrict SNP support on the > + * known CPU model and family for which the RMP table entry format is > + * currently defined for. > + */ > + if (!(c->x86 == 0x19 && c->x86_model <= 0xaf) && > + !(c->x86 == 0x1a && c->x86_model <= 0xf)) > + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); > + else if (!snp_probe_rmptable_info()) > + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); > + } IOW, this below. Lemme send the ZEN5 thing as a separate patch. diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 9492dcad560d..0fa702673e73 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -81,10 +81,8 @@ #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ - -/* CPU types for specific tunings: */ #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ -/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ +#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */ #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0f0d425f0440..46335c2df083 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -539,7 +539,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) /* Figure out Zen generations: */ switch (c->x86) { - case 0x17: { + case 0x17: switch (c->x86_model) { case 0x00 ... 0x2f: case 0x50 ... 0x5f: @@ -555,8 +555,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) goto warn; } break; - } - case 0x19: { + + case 0x19: switch (c->x86_model) { case 0x00 ... 0x0f: case 0x20 ... 0x5f: @@ -570,20 +570,31 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) goto warn; } break; - } + + case 0x1a: + switch (c->x86_model) { + case 0x00 ... 0x0f: + setup_force_cpu_cap(X86_FEATURE_ZEN5); + break; + default: + goto warn; + } + break; + default: break; } if (cpu_has(c, X86_FEATURE_SEV_SNP)) { /* - * RMP table entry format is not architectural and it can vary by processor + * RMP table entry format is not architectural, can vary by processor * and is defined by the per-processor PPR. Restrict SNP support on the * known CPU model and family for which the RMP table entry format is * currently defined for. */ - if (!(c->x86 == 0x19 && c->x86_model <= 0xaf) && - !(c->x86 == 0x1a && c->x86_model <= 0xf)) + if (!boot_cpu_has(X86_FEATURE_ZEN3) && + !boot_cpu_has(X86_FEATURE_ZEN4) && + !boot_cpu_has(X86_FEATURE_ZEN5)) setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); else if (!snp_probe_rmptable_info()) setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); @@ -1055,6 +1066,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); } +static void init_amd_zen5(struct cpuinfo_x86 *c) +{ + init_amd_zen_common(); +} + static void init_amd(struct cpuinfo_x86 *c) { u64 vm_cr; @@ -1100,6 +1116,8 @@ static void init_amd(struct cpuinfo_x86 *c) init_amd_zen3(c); else if (boot_cpu_has(X86_FEATURE_ZEN4)) init_amd_zen4(c); + else if (boot_cpu_has(X86_FEATURE_ZEN5)) + init_amd_zen5(c); /* * Enable workaround for FXSAVE leak on CPUs -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette