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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Dec 2023 16:44:57.1467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9f80bfd-07fa-4551-f92a-08dc0a1fd286 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017092.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9154 X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: EF327C000F X-Stat-Signature: coyy3z5iocgjo6stno1mery3f6btftjd X-Rspam-User: X-HE-Tag: 1704041102-473888 X-HE-Meta: U2FsdGVkX1+vBI0hY9yitPZA5j+sNYqEOAAgLko4pFs1+pDwC1AKPT0C2Jnyp+9V8iyM3Ahgf2Spd+1LfKNHqYmXa+DJ4/tp5mU/7lZwPsID4ccCfDeo6i0rtkZKZO3TVwvpvrL7tCgIXhkvsay0hdI/QXEYoCPp+VFj537duhAnjpkrGOWl+vdpxeDxs+U0lxptJMAl1rU81pz+03vFkF86m5jmFK7mXurn6UHAeLxWAY35X27us4/R6LhIn8bEO5FU26PLLaXkKoLnVABajtIcH4vVzkXtBNUxxBnmGPgTxxroBNGV++RTdg+FWoZ7lLC/a1Siuu821TP0dtzufx3T3tBxkt/iay6beN9ClgygQcOPVxGD85oVIIohsMcR4uTdlk37nB5T+LTsHPbi2GwA53p9ohob45q+BDUlpKrjgKxKedMweRCyo9TA/jFcLbFyHzOpyKq4ldXxrWBLiBfiRejF1bShTPxB2tOYCnp99TFuvy2YvGmXOvNR0XqAHMxDiQury5X6gXMghzXxl5pXHu5Tk3/CtFcFx4iPpXWI95+0wfOcbDVoAvOkHinKmnGPI0MidtQDzs7L6q2ilxXOkYd3HgnOoH3+NKZkXL77SH4jYOnyhG8DgfY6f3sBEWMIleq6DeVuEPV2kHE1E9xARd0vSYBoXI/XaSkjy+Hm5IfRozCnEpl0u48JEUO1jERmbs842woh8LSau90QH64NWhjI2tUN0OdNkTOnlvv6kHbLTJy9wnO52SRFGncR3simWqOsAizOMpcHQgR4Hxf1BM2us2cEbWlxqOZlnl9BXx4Ep+s5k7jU7L1BBnZg4wZD6MhuK37BAtS56ojo4bQwPnaDRCljMKQpwzqNfNgeqHm/BZFdGRD5pzrrX1bMuQG9i+jR114f9AXe8LTF61fphoFk3bpzt9rI2at7+dtOWBMaLfQbWN/NNZucG489vgDT+2YAL5j04Wi+uIq bHSvBWCR UlfczFidqvwbQBNSBeyrEOOHEgH1eNN7TVZaDB6wLpNQfdfglBvlmVjYJtOZA2wOXmqbtk/UW0c8x3Gdjxcw1GQcH1ZZfN2PZ3hbFHwZF94wQe/duM+DQIQ6uqKnDa1Rs//Yde/JFj1LrJvPf9bXUsgmWHzvbhwtLRFPNj9NTuoNOj5uv+3W87M3SESIsW9wNyc/UJZKrs/+8wUCVABZ4WtOzNBHYNUU8YcRLZfYrKw3lHm8NK5wGWtv29uCH5j6NS9YQn08cwPfuwWyBTcfGLCw0E0shUk7DNRU6VAbGZ5lGuuteNduLFCWshBC8LqWi4YyX6RgEqIwuI4gj4EAx3iXOUtJe/eNXAcJxauBjOyvkJWrJAafWLc1byMvQJT5jNYG2+akNfrf2OanLkul1s0lvFFJYC0SSPKw5xU//nCLL8+TdqrqLjXweJEvNg8NNN76/1xA1T+5UmCpHhx1c+04GXg== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Sun, Dec 31, 2023 at 12:50:12PM +0100, Borislav Petkov wrote: > On Sat, Dec 30, 2023 at 10:19:29AM -0600, Michael Roth wrote: > > From: Brijesh Singh > > > > Add CPU feature detection for Secure Encrypted Virtualization with > > Secure Nested Paging. This feature adds a strong memory integrity > > protection to help prevent malicious hypervisor-based attacks like > > data replay, memory re-mapping, and more. > > > > Since enabling the SNP CPU feature imposes a number of additional > > requirements on host initialization and handling legacy firmware APIs > > for SEV/SEV-ES guests, only introduce the CPU feature bit so that the > > relevant handling can be added, but leave it disabled via a > > disabled-features mask. > > > > Once all the necessary changes needed to maintain legacy SEV/SEV-ES > > support are introduced in subsequent patches, the SNP feature bit will > > be unmasked/enabled. > > > > Signed-off-by: Brijesh Singh > > Signed-off-by: Jarkko Sakkinen > > Signed-off-by: Ashish Kalra > > Signed-off-by: Michael Roth > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > arch/x86/include/asm/disabled-features.h | 4 +++- > > arch/x86/kernel/cpu/amd.c | 5 +++-- > > tools/arch/x86/include/asm/cpufeatures.h | 1 + > > 4 files changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index 29cb275a219d..9492dcad560d 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -442,6 +442,7 @@ > > #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ > > #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ > > #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ > > +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ > > #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ > > #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ > > #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* AMD SEV-ES full debug state swap support */ > > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > > index 702d93fdd10e..a864a5b208fa 100644 > > --- a/arch/x86/include/asm/disabled-features.h > > +++ b/arch/x86/include/asm/disabled-features.h > > @@ -117,6 +117,8 @@ > > #define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31)) > > #endif > > > > +#define DISABLE_SEV_SNP 0 > > I think you want this here if SEV_SNP should be initially disabled: > > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index a864a5b208fa..5b2fab8ad262 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -117,7 +117,7 @@ > #define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31)) > #endif > > -#define DISABLE_SEV_SNP 0 > +#define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) > > /* > * Make sure to add features to the correct mask Sorry, I must have inverted things when I was squashing in the changes =\ I've gone ahead and force-pushed your fixup to the snp-host-init-v1 branch. Thanks, Mike > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette