From: <shiju.jose@huawei.com>
To: <linux-cxl@vger.kernel.org>, <linux-mm@kvack.org>,
<dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dan.j.williams@intel.com>
Cc: <linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<david@redhat.com>, <Vilas.Sridharan@amd.com>,
<leo.duran@amd.com>, <Yazen.Ghannam@amd.com>,
<rientjes@google.com>, <jiaqiyan@google.com>,
<tony.luck@intel.com>, <Jon.Grimm@amd.com>,
<dave.hansen@linux.intel.com>, <rafael@kernel.org>,
<lenb@kernel.org>, <naoya.horiguchi@nec.com>,
<james.morse@arm.com>, <jthoughton@google.com>,
<somasundaram.a@hpe.com>, <erdemaktas@google.com>,
<pgonda@google.com>, <duenwen@google.com>,
<mike.malvestuto@intel.com>, <gthelen@google.com>,
<wschwartz@amperecomputing.com>, <dferguson@amperecomputing.com>,
<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
<kangkang.shen@futurewei.com>, <wanghuiqiang@huawei.com>,
<linuxarm@huawei.com>, <shiju.jose@huawei.com>
Subject: [PATCH v3 08/11] memory: scrub: Add scrub control attributes for the DDR5 ECS
Date: Fri, 24 Nov 2023 01:43:51 +0800 [thread overview]
Message-ID: <20231123174355.1176-9-shiju.jose@huawei.com> (raw)
In-Reply-To: <20231123174355.1176-1-shiju.jose@huawei.com>
From: Shiju Jose <shiju.jose@huawei.com>
Add scrub control attributes for the DDR5 ECS feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected data bits to the DRAM array
while providing transparency to error counts. The ECS control feature
allows the request to configure ECS input configurations during system
boot or at run-time.
The ECS control allows the requester to change the ECS threshold count
provided that the request is within the definition specified in DDR5 mode
registers, change mode between codeword mode and row count mode, and reset
the ECS counter.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/memory/scrub/memory-scrub.c | 13 ++++++++++++-
include/memory/memory-scrub.h | 10 ++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/scrub/memory-scrub.c b/drivers/memory/scrub/memory-scrub.c
index c2d794b2624b..43b7da43114f 100755
--- a/drivers/memory/scrub/memory-scrub.c
+++ b/drivers/memory/scrub/memory-scrub.c
@@ -208,7 +208,8 @@ static bool is_hex_attr(u32 attr)
static bool is_string_attr(u32 attr)
{
- return attr == scrub_speed_available;
+ return attr == scrub_speed_available ||
+ attr == scrub_threshold_available;
}
static struct attribute *scrub_genattr(const void *drvdata,
@@ -269,6 +270,16 @@ static const char * const scrub_common_attrs[] = {
[scrub_enable] = "enable",
[scrub_speed] = "speed",
[scrub_speed_available] = "speed_available",
+ /* scrub attributes - DDR5 ECS/common */
+ [scrub_ecs_log_entry_type] = "ecs_log_entry_type",
+ [scrub_ecs_log_entry_type_per_dram] = "ecs_log_entry_type_per_dram",
+ [scrub_ecs_log_entry_type_per_memory_media] = "ecs_log_entry_type_per_memory_media",
+ [scrub_mode] = "mode",
+ [scrub_mode_counts_rows] = "mode_counts_rows",
+ [scrub_mode_counts_codewords] = "mode_counts_codewords",
+ [scrub_reset_counter] = "reset_counter",
+ [scrub_threshold] = "threshold",
+ [scrub_threshold_available] = "threshold_available",
};
static struct attribute **
diff --git a/include/memory/memory-scrub.h b/include/memory/memory-scrub.h
index d7cbde4718d0..74ad5addd5b3 100755
--- a/include/memory/memory-scrub.h
+++ b/include/memory/memory-scrub.h
@@ -23,6 +23,16 @@ enum scrub_attributes {
scrub_enable,
scrub_speed,
scrub_speed_available,
+ /* scrub attributes - DDR5 ECS/common */
+ scrub_ecs_log_entry_type,
+ scrub_ecs_log_entry_type_per_dram,
+ scrub_ecs_log_entry_type_per_memory_media,
+ scrub_mode,
+ scrub_mode_counts_rows,
+ scrub_mode_counts_codewords,
+ scrub_reset_counter,
+ scrub_threshold,
+ scrub_threshold_available,
max_attrs,
};
--
2.34.1
next prev parent reply other threads:[~2023-11-23 17:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-23 17:43 [PATCH v3 00/11] cxl: Add support for CXL feature commands, CXL device patrol scrub control and DDR5 ECS control features shiju.jose
2023-11-23 17:43 ` [PATCH v3 01/11] cxl/mbox: Add GET_SUPPORTED_FEATURES mailbox command shiju.jose
2023-11-24 13:20 ` kernel test robot
2023-11-24 16:05 ` Shiju Jose
2023-11-23 17:43 ` [PATCH v3 02/11] cxl/mbox: Add GET_FEATURE " shiju.jose
2023-11-24 15:23 ` kernel test robot
2023-11-23 17:43 ` [PATCH v3 03/11] cxl/mbox: Add SET_FEATURE " shiju.jose
2023-11-23 17:43 ` [PATCH v3 04/11] cxl/memscrub: Add CXL device patrol scrub control feature shiju.jose
2023-11-23 17:43 ` [PATCH v3 05/11] cxl/memscrub: Add CXL device DDR5 ECS " shiju.jose
2023-11-23 17:43 ` [PATCH v3 06/11] memory: scrub: Add scrub driver supports configuring memory scrubs in the system shiju.jose
2023-11-23 17:43 ` [PATCH v3 07/11] cxl/memscrub: Register CXL device patrol scrub with scrub configure driver shiju.jose
2023-11-23 17:43 ` shiju.jose [this message]
2023-11-23 17:43 ` [PATCH v3 09/11] cxl/memscrub: Register CXL device DDR5 ECS " shiju.jose
2023-11-23 17:43 ` [PATCH v3 10/11] memory: scrub: sysfs: Add Documentation for set of common scrub attributes shiju.jose
2023-11-23 17:43 ` [PATCH v3 11/11] cxl: scrub: sysfs: Add Documentation for CXL memory device scrub control attributes shiju.jose
2023-11-24 14:39 ` kernel test robot
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