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X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="13650949" X-IronPort-AV: E=Sophos;i="6.04,219,1695711600"; d="scan'208";a="13650949" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2023 09:34:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,219,1695711600"; d="scan'208";a="8565768" Received: from lkp-server01.sh.intel.com (HELO d584ee6ebdcc) ([10.239.97.150]) by fmviesa002.fm.intel.com with ESMTP; 22 Nov 2023 09:34:47 -0800 Received: from kbuild by d584ee6ebdcc with local (Exim 4.96) (envelope-from ) id 1r5r7c-0000jR-1H; Wed, 22 Nov 2023 17:34:44 +0000 Date: Thu, 23 Nov 2023 01:34:04 +0800 From: kernel test robot To: Samuel Holland , Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Samuel Holland Subject: Re: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Message-ID: <202311222306.siw2cvCj-lkp@intel.com> References: <20231122010815.3545294-4-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231122010815.3545294-4-samuel.holland@sifive.com> X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 9D5991C0012 X-Stat-Signature: iph6ep3mij5sthd3c63piutcrr7eprx1 X-Rspam-User: X-HE-Tag: 1700674490-45734 X-HE-Meta: U2FsdGVkX193i9qrAe5/9tawxic5XPnj76Wh1f6i7Bomf3BPrSNl0+i8Ak8Fl/UeXYgWpCDzK/EsLxET/GJL6wUm/5fLsIlVZgISUj2G0eIXDohii30iFZ6OnQQuVtLWxzFtVZB3oxDlvKf3uW4JFTYOmH2unqclIxYUEInAoiB7ELMFh7ADKtO+3fVRYNv5WYMAagkv5qPOVAz265g60RKdB6AKXps+ewLn5PbKwLfAI/0a3vXW9Li9QHjwAGfuyUk89i+qvHXLY1MXc+pGy2r3XqmKGIGSeh5v5QZBX24CnX7OmMvoeUhp8aQn4QAo8HpPmFIL8OMQ1dkFEsa3Iv5YexMiTGdNrHXJCcuPeB2hlBjxfnGARQnDJAM1W/kWH/8pGAjwn0aWaN+Uq1pmcbLgyhtK/Pg17p2Rkyqm7u3CkBG9f4sNU8O98zFgGuBlsRRSGNtDmDoHc1JBw7x7jRSQSl4kh2saQkmnN6i82TFGVQqe3eKzv1dYmPU3XTHb2PocQPgISYt7Af/lpskzWU7BgQ9eAz+jo0drUv7hY41OyEx2qavXrR4WjqK1XyUogW55LyPXoyYZ61DSpg4ypVTYrvQJQnSJJKq5OGCLDq/g4LsrP4rqesx0IvIwzIG2u5UWS2Yb/zy2sPclMSvOlW7gV+pQ7QD2IgszXftJrYzftOaUH4S7KFzHAcJb+BZnnknrI1pNOq01Gl/A1OAaXV85cMygl3kJBjKIwOER3gnfIlKmt1PNAksYVubllmFFEj6AA62HsBopFgv/aCA1O+uddpL3vJe9MtkO6pJPr3JJfqu65gTs4dNtvyKHhden8JvYnlWsvd07LgLVNL4M8x4C6Xzx8Jzbj1zwIWcIMgQqSLCpKX8uPf5JckZ4Id/jTJsLhz1VMzrqF7hr4q9S1jgEkQEnJnlGqqMTfbMo3TZerN7h0QjmDzWkAf0WwV8k91K9Dgs6iE9jSAq6dXS mZqckT8g 2VA6LcODwKMPXvb4ucs0jiYG9ndELFBXrcIwrdqGBDvZNkQVJNjjPupXxJxfuH7w0oRqR8/YHZRmz/anm9OLlXqelaS1kzicMZ12fGfCiSd5F8ijfFJ8FokaEE3CZhO+A3TkaZB4c435p3c2RlzvW1h4ilD3IAvXYaDqn2SJTW//YYsWRKJGu9j4GMH3DjgtPkeT0S2G5BHbbmNhEORICax0JIM9jY2CcZC1ludHC1eobcgeTF/qCPsImf2LYW70WwOa7BNW+4eRg5yAINmlIL5w5spQ8jVdLVtznUGXxayuqPxkSMccSPQM5+iV5djDX7o1HK7Dy164reMuN6EV4VJ86Y88kcngEpERXTYPXWN17M60IZJGh27W3uJGTwI3bVQjJQCIxdOyK9hmzP9Pq893AyTcv+z+EdDneBuJ5wKQQVdQ= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000001, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Samuel, kernel test robot noticed the following build errors: [auto build test ERROR on linus/master] [also build test ERROR on v6.7-rc2 next-20231122] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/riscv-mm-Combine-the-SMP-and-UP-TLB-flush-code/20231122-091249 base: linus/master patch link: https://lore.kernel.org/r/20231122010815.3545294-4-samuel.holland%40sifive.com patch subject: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 config: riscv-randconfig-001-20231122 (https://download.01.org/0day-ci/archive/20231122/202311222306.siw2cvCj-lkp@intel.com/config) compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231122/202311222306.siw2cvCj-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202311222306.siw2cvCj-lkp@intel.com/ All errors (new ones prefixed by >>): >> arch/riscv/errata/sifive/errata.c:46:2: error: use of undeclared identifier 'tlb_flush_all_threshold' tlb_flush_all_threshold = 0; ^ 1 error generated. vim +/tlb_flush_all_threshold +46 arch/riscv/errata/sifive/errata.c 33 34 static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long impid) 35 { 36 /* 37 * Affected cores: 38 * Architecture ID: 0x8000000000000007 or 0x1 39 * Implement ID: mimpid[23:0] <= 0x200630 and mimpid != 0x01200626 40 */ 41 if (arch_id != 0x8000000000000007 && arch_id != 0x1) 42 return false; 43 if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626) 44 return false; 45 > 46 tlb_flush_all_threshold = 0; 47 48 return true; 49 } 50 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki