From: kernel test robot <lkp@intel.com>
To: Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
Date: Thu, 23 Nov 2023 01:34:04 +0800 [thread overview]
Message-ID: <202311222306.siw2cvCj-lkp@intel.com> (raw)
In-Reply-To: <20231122010815.3545294-4-samuel.holland@sifive.com>
Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.7-rc2 next-20231122]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/riscv-mm-Combine-the-SMP-and-UP-TLB-flush-code/20231122-091249
base: linus/master
patch link: https://lore.kernel.org/r/20231122010815.3545294-4-samuel.holland%40sifive.com
patch subject: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
config: riscv-randconfig-001-20231122 (https://download.01.org/0day-ci/archive/20231122/202311222306.siw2cvCj-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231122/202311222306.siw2cvCj-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311222306.siw2cvCj-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/riscv/errata/sifive/errata.c:46:2: error: use of undeclared identifier 'tlb_flush_all_threshold'
tlb_flush_all_threshold = 0;
^
1 error generated.
vim +/tlb_flush_all_threshold +46 arch/riscv/errata/sifive/errata.c
33
34 static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long impid)
35 {
36 /*
37 * Affected cores:
38 * Architecture ID: 0x8000000000000007 or 0x1
39 * Implement ID: mimpid[23:0] <= 0x200630 and mimpid != 0x01200626
40 */
41 if (arch_id != 0x8000000000000007 && arch_id != 0x1)
42 return false;
43 if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626)
44 return false;
45
> 46 tlb_flush_all_threshold = 0;
47
48 return true;
49 }
50
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2023-11-22 17:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 1:07 [PATCH v3 0/8] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-11-22 1:07 ` [PATCH v3 1/8] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2023-11-22 1:07 ` [PATCH v3 2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-11-22 1:07 ` [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2023-11-22 17:34 ` kernel test robot [this message]
2023-11-22 1:07 ` [PATCH v3 4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-11-22 1:07 ` [PATCH v3 5/8] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-11-22 1:07 ` [PATCH v3 6/8] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-11-22 1:07 ` [PATCH v3 7/8] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-11-22 1:07 ` [PATCH v3 8/8] riscv: mm: Always use ASID to flush MM contexts Samuel Holland
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