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Tue, 21 Nov 2023 17:08:21 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id bn5-20020a056a00324500b006be047268d5sm8713961pfb.174.2023.11.21.17.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 17:08:20 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Samuel Holland Subject: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Date: Tue, 21 Nov 2023 17:07:14 -0800 Message-ID: <20231122010815.3545294-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122010815.3545294-1-samuel.holland@sifive.com> References: <20231122010815.3545294-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 80997180008 X-Stat-Signature: p44c6ae3bo13uzkmc5xzu1adi1yrrgub X-HE-Tag: 1700615302-529068 X-HE-Meta: U2FsdGVkX19PRNo68tU7SHR51HWap2TcPPtCIz0fGE3MvKEbM/5Cc4QbvozAJ/T4VH9Qz4Da9BAubBkXiR0y8adJ0fU8dAX4CBJ75hBxbSydNuLIzU6/c7UiMmPirZMA/i58Xl4Omp7ZAHtZ0XBCD5vFIMVkhLuQRZH35AqIh5PFBqtL2lY0S+lEJpgKjVzQhZzshWGuujXBDxA8VYMQnC2TDFo8y0DUsoH51/erg7brugotbZqKXkrw/nC+YoTNs5W+iimXVFcNfJOiRliMQbjbsc+PIZnnSUodN+CwQWo93gSHxUNfDr7KhOU2Au7+7nvQGVxEh8lmNi0iYQfMS0apRhUYiDsyVa/DMZ3RO2mv+6YLASroWCYtSK1ohFwZSAwTDR63j5khmCJs19k1KeQc2e5boHf9m0YvQCn2/aDuQmnGDAxz1IGuCbesTWqgZTL2Tkn6+7efE5dC57pmYI4SQ/MGt0b224bBBKysq88rsYoTcrvQdzIx5ue6GJVSwp0GXvWFUD5K8N8ai5Scbx0Qj+DWVt3lby3cjmvqxGjM4ub/qiqkEXR8+VCEBI2LJbhiPw1eRTKGsByOZfEUoEzijMR4pnB6+PNTlJ1oWxtaO6IVZnhWPNvcw37sPIadeKJzAB6+SQE3/7TIlC9VkF3HWrroOvH/9OO7h3zp3bC5+z296MvG2iX6YrJ+8iWL/gMyVwaP58v+feNuylDza4w5f3WknbpzDi9gLoCWxmBUcGEZxItGEOFeo/ROLoo+66uuwvoBEeyA+LYfNZKqRHuw2BLHkO6ykw2JTINdznM6ius7CExeb/hEJj44ISmQj/PnBrIzUJ+elqUF6exaeN3KIfzRHMjIiqoNxz0DJ1x7AK9DoTVLKnUAJqjtDARxW8NpU5EEheGQcpWTbMb7ncpfvjorvXco01mHCnQ3FjWgLRDfYg1hQTQ3yc97uwnDBcQ7uySYyHe8kD5xj7M KB7L84hN d5KBh9gUtvuTlPiC1Q61bzqPzcF9bQJTiwo3ER4p0X5xFVd0a3gNjMSVCc0y27B94y0wQDUGDYAyfuHcKG9XSXyorOGDUCdwHuDiAyn8nU/1ANMCs1DW4r43BMHhYkIXRksAx/jJl0dML6WgBCvB/Pj+ovPzcp5L8BP0euPI69DvZ+76816GiPnM5ZnZLxuRlGi+Vjyyy0aGVDdYx8aLdrSHZ1SHABBbwoFJ4/cY/HrkJkBbv4xFeCLSI6HS5AuqxJDJC1XTve2S3T9xHSHKCbQCm4wsuOR51E9PtIC15q+JJIXnIsILQymPYTu7ijlbbMXM7WFHSzoqaJmIcqgIBh8w4z9zmGMAhnoeaLLVJouZXIj00y2lz3kwQ99J5lfrKd4Rduxw01siIMBk= X-Bogosity: Ham, tests=bogofilter, spamicity=0.003160, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Since implementations affected by SiFive errata CIP-1200 always use the global variant of the sfence.vma instruction, they only need to execute the instruction once. The range-based loop only hurts performance. Signed-off-by: Samuel Holland --- Changes in v3: - New patch for v3 arch/riscv/errata/sifive/errata.c | 3 +++ arch/riscv/include/asm/tlbflush.h | 2 ++ arch/riscv/mm/tlbflush.c | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 3d9a32d791f7..00e011d78866 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -42,6 +42,9 @@ static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long imp return false; if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626) return false; + + tlb_flush_all_threshold = 0; + return true; } diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index e529a643be17..3b393f765805 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -62,6 +62,8 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end); void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); #endif + +extern unsigned long tlb_flush_all_threshold; #else /* CONFIG_MMU */ #define local_flush_tlb_all() do { } while (0) #endif /* CONFIG_MMU */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 0feccb8932d2..27b3744b5673 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -11,7 +11,7 @@ * Flush entire TLB if number of entries to be flushed is greater * than the threshold below. */ -static unsigned long tlb_flush_all_threshold __read_mostly = 64; +unsigned long tlb_flush_all_threshold __read_mostly = 64; static void local_flush_tlb_range_threshold_asid(unsigned long start, unsigned long size, -- 2.42.0