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b=FEMrcBpmVAZPEUpoDRtVydDNhsKOFOzZh59NstRt2tkZ8Vi1A8sjRQDPvCAieE6Ef HNyTpNW+M6Lxv7CokklY0WGv33hBj2LS2IjxKca8R6dEL0ffa7S7DodpgrrE1b5OiC L7Cn0m9BOFR40PMFSDm85v5nJEy6hMNR166YPfVLiPo5kUFZgCioS2eSZ0IJIK2JYm kv8QeKZ4hEn1mhrGnWxc+xtTu8QXzwyF7S84Crt/R6gdI/w/zTWJhUqfbABWTGfSji cMzB8QwL0teO+2Zy9IVUTQ9DyGUrmc2ja3ex34h+X6nYFsBQ+1pkLWNb4HoI00hn8m e6M6KIK8Ut0xA== Date: Tue, 7 Nov 2023 10:12:21 +0000 From: Will Deacon To: "Yin, Fengwei" Cc: Barry Song <21cnbao@gmail.com>, Baolin Wang , catalin.marinas@arm.com, akpm@linux-foundation.org, v-songbaohua@oppo.com, yuzhao@google.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: mm: drop tlb flush operation when clearing the access bit Message-ID: <20231107101221.GB18944@willie-the-truck> References: <44e32b0e-0e41-4055-bdb9-15bc7d47197c@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44e32b0e-0e41-4055-bdb9-15bc7d47197c@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Rspam-User: X-Stat-Signature: n7og6rud6cuzrdyirebsrcojz7wknstk X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 7A2DF20008 X-HE-Tag: 1699351948-246037 X-HE-Meta: U2FsdGVkX1/z6dqstBxqqo5DwbeaqS7qw3FxVBFf5X5ycdBqUxR9ESNjDKY2q+2Rk5gcmf4W+txYdIIT3llHYpX2exUyu8HNss6KhFsv3P+R8HHQHz03bHiEn5v3jt0BWT3LFLEJJhLazjsquYCGEbLz5FFiDJ5Ba3s1sO7TFTKrpZ6EJRBDnY3RC4bj+xpM9Dg2WBSsgVYG9FkzYXQ9XppfztMYqZTq814mX9jOu7WI6UN6Nj4cW8abE3TjCSTYeVP3j0MruVUdND9M6QqpegZBvd/zjHYTCAaCiRbavMGZJiWh3sLGlsyLCrj4MnKNANb7slDwZjmtVRbDU5TZIs83mSbjcOIw9Yucd7rfSa/hBv+PO3l4CYuzelyvgdniQrh6j09BimWczWjb+iIdTlrzr/xNa3SMQFyICriflFdaagAMKLd6qOWRCpxYah4frToaOGYCvmpFCSSaKDm3aQVe5o3MUzDIBDdgG0tniA9KuSqA+Szi7xLaNjv0vNwatv5OLyAtdqSjerle4K4w3Fho7JOTjGYxQzbalLo1/noqtzl7RWvJsW0MxpAaS/e9o/aPlBv4zSOacoic9k7Em0PpOqFfDZ9Hiv1rDyr6B0eMw3f86YSeUOr08/FqaDa3R7gaWduM+7v9VEqpOPnQyyfv8gLjomj6g1N0vsit1+1TgL0GTIvMXLWzZVwhITKVl3j/6qYuEI4r63pY0m/0d7qCvAeMkjaeJdVgw7X7LZhfBQY5t3Ffk0vvlc9OMD/PwBbZimutLcxEF9Z+CwG+ENjjpg4rgQK3YA4ugP9ze8lmIBVIoS5aClchQWOlFWtG4DWeZTieiCYmxHSni9Z8mTsvOuh8rwDdPKoITlsv9JV0BtPN/4Zg+jOi3GGkELdc2U9Jz3rtR25Ego+F/Zi2G/+rfzsDk2EdJoAyYRESA6QrcdfkwefAdD2AnRQOLAaskD4td7eezgbWELwyI7F 0PTlGMtm jY9khjoVBtKRBP75OnMJn3sXLRxZa2J9eICrJcgbgHgWZxevmvFTTzwkvUxG74BrhEKocp4mP9fDjSurh/QYYWk03XBMP6vLu2vgl/Qpk4TdEjnhlpLMEmx4GDloFEK5ssLSuzauypKSGjr9bbAjz4Yumhj40wus2v6xE13PFWLEhH2+LYZBusyYhYcK0TK2pZDPwk9Gs/TQ8KGb/F86Gm2u1hD+01tVv1ltPPY/38qECZRjj6lDyllXEEUus+Rn9B1WMlHUK+NPowlUmo69OLGWJsmhmQub7CzC1/QkPnNVEm3tLtzBSgyjf8A== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Wed, Oct 25, 2023 at 09:39:19AM +0800, Yin, Fengwei wrote: > > >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > >> index 0bd18de9fd97..2979d796ba9d 100644 > >> --- a/arch/arm64/include/asm/pgtable.h > >> +++ b/arch/arm64/include/asm/pgtable.h > >> @@ -905,21 +905,22 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, > >> static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > >> unsigned long address, pte_t *ptep) > >> { > >> - int young = ptep_test_and_clear_young(vma, address, ptep); > >> - > >> - if (young) { > >> - /* > >> - * We can elide the trailing DSB here since the worst that can > >> - * happen is that a CPU continues to use the young entry in its > >> - * TLB and we mistakenly reclaim the associated page. The > >> - * window for such an event is bounded by the next > >> - * context-switch, which provides a DSB to complete the TLB > >> - * invalidation. > >> - */ > >> - flush_tlb_page_nosync(vma, address); > >> - } > >> - > >> - return young; > >> + /* > >> + * This comment is borrowed from x86, but applies equally to ARM64: > >> + * > >> + * Clearing the accessed bit without a TLB flush doesn't cause > >> + * data corruption. [ It could cause incorrect page aging and > >> + * the (mistaken) reclaim of hot pages, but the chance of that > >> + * should be relatively low. ] > >> + * > >> + * So as a performance optimization don't flush the TLB when > >> + * clearing the accessed bit, it will eventually be flushed by > >> + * a context switch or a VM operation anyway. [ In the rare > >> + * event of it not getting flushed for a long time the delay > >> + * shouldn't really matter because there's no real memory > >> + * pressure for swapout to react to. ] > >> + */ > >> + return ptep_test_and_clear_young(vma, address, ptep); > >> } > From https://lore.kernel.org/lkml/20181029105515.GD14127@arm.com/: > > This is blindly copied from x86 and isn't true for us: we don't invalidate > the TLB on context switch. That means our window for keeping the stale > entries around is potentially much bigger and might not be a great idea. I completely agree. > My understanding is that arm64 doesn't do invalidate the TLB during > context switch. The flush_tlb_page_nosync() here + DSB during context > switch make sure the TLB is invalidated during context switch. > So we can't remove flush_tlb_page_nosync() here? Or something was changed > for arm64 (I have zero knowledge to TLB on arm64. So some obvious thing > may be missed)? Thanks. As you point out, we already elide the DSB here but I don't think we should remove the TLB invalidation entirely because then we lose the guarantee that the update ever becomes visible to the page-table walker. I'm surprised that the TLBI is showing up as a performance issue without the DSB present. Is it because we're walking over a large VA range and invalidating on a per-page basis? If so, we'd be better off batching them up and doing the invalidation at the end (which will be upgraded to a full-mm invalidation if the range is large enough). Will