From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Andrew Jones <ajones@ventanamicro.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v2 01/11] riscv: Improve tlb_flush()
Date: Sat, 28 Oct 2023 16:11:59 -0700 [thread overview]
Message-ID: <20231028231339.3116618-2-samuel.holland@sifive.com> (raw)
In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com>
From: Alexandre Ghiti <alexghiti@rivosinc.com>
For now, tlb_flush() simply calls flush_tlb_mm() which results in a
flush of the whole TLB. So let's use mmu_gather fields to provide a more
fine-grained flush of the TLB.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # On RZ/Five SMARC
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Changes in v2:
- Rebase on Alexandre's "riscv: tlb flush improvements" series v5
arch/riscv/include/asm/tlb.h | 8 +++++++-
arch/riscv/include/asm/tlbflush.h | 3 +++
arch/riscv/mm/tlbflush.c | 7 +++++++
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h
index 120bcf2ed8a8..1eb5682b2af6 100644
--- a/arch/riscv/include/asm/tlb.h
+++ b/arch/riscv/include/asm/tlb.h
@@ -15,7 +15,13 @@ static void tlb_flush(struct mmu_gather *tlb);
static inline void tlb_flush(struct mmu_gather *tlb)
{
- flush_tlb_mm(tlb->mm);
+#ifdef CONFIG_MMU
+ if (tlb->fullmm || tlb->need_flush_all)
+ flush_tlb_mm(tlb->mm);
+ else
+ flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end,
+ tlb_get_unmap_size(tlb));
+#endif
}
#endif /* _ASM_RISCV_TLB_H */
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index a09196f8de68..f5c4fb0ae642 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -32,6 +32,8 @@ static inline void local_flush_tlb_page(unsigned long addr)
#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
void flush_tlb_all(void);
void flush_tlb_mm(struct mm_struct *mm);
+void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
+ unsigned long end, unsigned int page_size);
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
@@ -52,6 +54,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
}
#define flush_tlb_mm(mm) flush_tlb_all()
+#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
#endif /* !CONFIG_SMP || !CONFIG_MMU */
/* Flush a range of kernel pages */
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 77be59aadc73..fa03289853d8 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -132,6 +132,13 @@ void flush_tlb_mm(struct mm_struct *mm)
__flush_tlb_range(mm, 0, -1, PAGE_SIZE);
}
+void flush_tlb_mm_range(struct mm_struct *mm,
+ unsigned long start, unsigned long end,
+ unsigned int page_size)
+{
+ __flush_tlb_range(mm, start, end - start, page_size);
+}
+
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
__flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
--
2.42.0
next prev parent reply other threads:[~2023-10-28 23:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-28 23:11 [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-10-28 23:11 ` Samuel Holland [this message]
2023-10-28 23:12 ` [PATCH v2 02/11] riscv: Improve flush_tlb_range() for hugetlb pages Samuel Holland
2023-10-28 23:12 ` [PATCH v2 03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Samuel Holland
2023-10-28 23:12 ` [PATCH v2 04/11] riscv: Improve flush_tlb_kernel_range() Samuel Holland
2023-10-28 23:12 ` [PATCH v2 05/11] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2023-10-28 23:12 ` [PATCH v2 06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-10-28 23:12 ` [PATCH v2 07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-10-28 23:12 ` [PATCH v2 08/11] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-10-28 23:12 ` [PATCH v2 09/11] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-10-28 23:12 ` [PATCH v2 10/11] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-10-28 23:12 ` [PATCH v2 11/11] riscv: mm: Always use ASID to flush MM contexts Samuel Holland
2023-11-07 6:50 ` [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements patchwork-bot+linux-riscv
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