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From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v2 11/11] riscv: mm: Always use ASID to flush MM contexts
Date: Sat, 28 Oct 2023 16:12:09 -0700	[thread overview]
Message-ID: <20231028231339.3116618-12-samuel.holland@sifive.com> (raw)
In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com>

Even if multiple ASIDs are not supported, using the single-ASID variant
of the sfence.vma instruction preserves TLB entries for global (kernel)
pages. So it is always most efficient to use the single-ASID code path.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

Changes in v2:
 - Update both copies of __flush_tlb_range()

 arch/riscv/include/asm/mmu_context.h | 2 --
 arch/riscv/mm/context.c              | 3 +--
 arch/riscv/mm/tlbflush.c             | 5 ++---
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
index 7030837adc1a..b0659413a080 100644
--- a/arch/riscv/include/asm/mmu_context.h
+++ b/arch/riscv/include/asm/mmu_context.h
@@ -33,8 +33,6 @@ static inline int init_new_context(struct task_struct *tsk,
 	return 0;
 }
 
-DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
-
 #include <asm-generic/mmu_context.h>
 
 #endif /* _ASM_RISCV_MMU_CONTEXT_H */
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index 3ca9b653df7d..20057085ab8a 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -18,8 +18,7 @@
 
 #ifdef CONFIG_MMU
 
-DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
-
+static DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
 static unsigned long num_asids;
 
 static atomic_long_t current_version;
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 1cfac683bda4..9d06a3e9d330 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -90,8 +90,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 		/* check if the tlbflush needs to be sent to other CPUs */
 		broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
 
-		if (static_branch_unlikely(&use_asid_allocator))
-			asid = cntx2asid(atomic_long_read(&mm->context.id));
+		asid = cntx2asid(atomic_long_read(&mm->context.id));
 	} else {
 		cmask = cpu_online_mask;
 		broadcast = true;
@@ -122,7 +121,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 {
 	unsigned long asid = FLUSH_TLB_NO_ASID;
 
-	if (mm && static_branch_unlikely(&use_asid_allocator))
+	if (mm)
 		asid = cntx2asid(atomic_long_read(&mm->context.id));
 
 	local_flush_tlb_range_asid(start, size, stride, asid);
-- 
2.42.0



  parent reply	other threads:[~2023-10-28 23:14 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-28 23:11 [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-10-28 23:11 ` [PATCH v2 01/11] riscv: Improve tlb_flush() Samuel Holland
2023-10-28 23:12 ` [PATCH v2 02/11] riscv: Improve flush_tlb_range() for hugetlb pages Samuel Holland
2023-10-28 23:12 ` [PATCH v2 03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Samuel Holland
2023-10-28 23:12 ` [PATCH v2 04/11] riscv: Improve flush_tlb_kernel_range() Samuel Holland
2023-10-28 23:12 ` [PATCH v2 05/11] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2023-10-28 23:12 ` [PATCH v2 06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-10-28 23:12 ` [PATCH v2 07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-10-28 23:12 ` [PATCH v2 08/11] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-10-28 23:12 ` [PATCH v2 09/11] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-10-28 23:12 ` [PATCH v2 10/11] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-10-28 23:12 ` Samuel Holland [this message]
2023-11-07  6:50 ` [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements patchwork-bot+linux-riscv

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