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a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1698430157; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bvKLcx4hGTswbkqy0wzc53Fs4hwT/BZ1For+XMgMmEQ=; b=wpksmO50kf5povT0plAFsQ9JXR6ytJcntKdfB4zJ7qEgUOGAU/iEn780aDg9kpHfHAx10j 3XR2XV7BxCa5AQ9wWjKo9CbNu7dpIRpFZoMPIw7MBtqgOjI4MQrCpTSslda7rWWSfzsXr3 P1zq8dBni8istZJj4wFzvErNCzpuVw4= Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 153751424; Fri, 27 Oct 2023 11:09:58 -0700 (PDT) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 47BF93F64C; Fri, 27 Oct 2023 11:09:14 -0700 (PDT) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com, broonie@kernel.org, catalin.marinas@arm.com, dave.hansen@linux.intel.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, James Morse , Suzuki K Poulose , Zenghui Yu Subject: [PATCH v2 05/24] arm64: context switch POR_EL0 register Date: Fri, 27 Oct 2023 19:08:31 +0100 Message-Id: <20231027180850.1068089-6-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231027180850.1068089-1-joey.gouly@arm.com> References: <20231027180850.1068089-1-joey.gouly@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: 4C9904000D X-Stat-Signature: eywtjcytzyokxgpc1tfn3u7jrpobh7g5 X-Rspam-User: X-HE-Tag: 1698430157-756436 X-HE-Meta: U2FsdGVkX19ZIKBhtnrMKsEi696gKrsbhsZ+DZXjGeCtSjWPM3Wm5R7253o+oUBKtWu8u+9PnwHnSl555bAYhL/nKvvQy84h0NeijZQpb9PU4lof52/bEdsRKPF/M3IM3XnUuPxv8k/QP1RBSjNkAVbw7+AFpJOhdHAHrsYMYcGWyC7HRj01Ao8osXVc77AmOn1iIisHX4831d6kbpyVwxgA8P41gnOXxMmSlnoEedpSAdCbSkxrImb7PkapqtABiuJj27hRGAzmPvTYD6v/xqS1Fggt279FAl2YqIn11T+whdHahmdRPRDbTLio7JK+66j6OM9Y/4bcEnPwlfftOsNYd+lR5OIX8GgfFRrfKS51O0jb6MNgwHVdQMbX0eQ40w6umg1cHQCat7TRYvFCjOQSdmgHV23e6ZMnw2IziR48zDA2QU9UM+Q6hayx8QsNWYY1Guyhhm/EOfeTTwsnfjWLLH7nsD+jXOKoegq6XSoZD4TeVWFGUdooKmYwlGWN9anz1xZcnE14BS1+Dn9W9dZjH+HLu0LRlYR/OgUMsImXufX527tS7OJCsDVewSWQwgPCXT4KVgU8kcMMoI/BmdwUkUf6+zRdMt2W5nuRzwTWRCSGn9ZmfC16M2j9zcCcsciQvMzytHouslxcy9BBonEqWSPipmz7N5FbLfuEE7saWntgVECXmKqNfSHgqx5+kqFUOWVUpzIyDyqP7utNuPUEMJ2wx41sahVKoVTFYVUYCiyXyl2YZDJi8zsmEhTLVy8qJ9O8e7YInuJYcY61OYfJ7F8gdc3A7zEzbfohNJ0TFjYXJcqlYOAv3Q+braomowpcKmTkZe3g6Mw/xSEx1nuXW2H8CwMHK3zpHWAn7pqQmu/C/BTBCni+iecIMvjWblr+3/MYt4rITuKJ0F7Q2vsyOaUOBSmSH3DDXtctaTlUjMA/bQd2EwnQAHYPTT7eXBi5I2201Yf13jDxj9H LZus3L38 9SkCn3M/U7GwMFQmp+IbxLoIM9l3xuiZ1qxWGB8ZiIAF3/OmYGHBCXBBob1VoEl5NONOuq8g3knHZu/lA3QN02haq9dNrIUf9UQTLq56t8gDzkJJa8jtcQ5iWrlKk7vOupMGSelZ/LUlH8u+oFRs+NOb3beWpnBWIFGD5kH0bAV6i4nEREUTwAGkUOfOvwSBUevyzUUDgAk+V4kuAlnt8eiM37AjL8EGPNGhAp0fbVWnHQUJVmZsBlemV3SCe36JFssyYIehDo0DqY/4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: POR_EL0 is a register that can be modified by userspace directly, so it must be context switched. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/cpufeature.h | 6 ++++++ arch/arm64/include/asm/processor.h | 1 + arch/arm64/include/asm/sysreg.h | 3 +++ arch/arm64/kernel/process.c | 19 +++++++++++++++++++ 4 files changed, 29 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 5bba39376055..019af90a3cf4 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -831,6 +831,12 @@ static inline bool system_supports_tlb_range(void) cpus_have_const_cap(ARM64_HAS_TLB_RANGE); } +static inline bool system_supports_poe(void) +{ + return IS_ENABLED(CONFIG_ARM64_POE) && + alternative_has_cap_unlikely(ARM64_HAS_S1POE); +} + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index e5bc54522e71..b3ad719c2d0c 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -179,6 +179,7 @@ struct thread_struct { u64 sctlr_user; u64 svcr; u64 tpidr2_el0; + u64 por_el0; }; static inline unsigned int thread_get_vl(struct thread_struct *thread, diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cc2d61fd45c3..32270823a40b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1007,6 +1007,9 @@ #define POE_RXW UL(0x7) #define POE_MASK UL(0xf) +/* Initial value for Permission Overlay Extension for EL0 */ +#define POR_EL0_INIT POE_RXW + #define ARM64_FEATURE_FIELD_BITS 4 /* Defined for compatibility only, do not add new users. */ diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 0fcc4eb1a7ab..9caed797fc47 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -271,12 +271,19 @@ static void flush_tagged_addr_state(void) clear_thread_flag(TIF_TAGGED_ADDR); } +static void flush_poe(void) +{ + if (system_supports_poe()) + write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0); +} + void flush_thread(void) { fpsimd_flush_thread(); tls_thread_flush(); flush_ptrace_hw_breakpoint(current); flush_tagged_addr_state(); + flush_poe(); } void arch_release_task_struct(struct task_struct *tsk) @@ -498,6 +505,17 @@ static void erratum_1418040_new_exec(void) preempt_enable(); } +static void permission_overlay_switch(struct task_struct *next) +{ + if (system_supports_poe()) { + current->thread.por_el0 = read_sysreg_s(SYS_POR_EL0); + if (current->thread.por_el0 != next->thread.por_el0) { + write_sysreg_s(next->thread.por_el0, SYS_POR_EL0); + isb(); + } + } +} + /* * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore * this function must be called with preemption disabled and the update to @@ -533,6 +551,7 @@ struct task_struct *__switch_to(struct task_struct *prev, ssbs_thread_switch(next); erratum_1418040_thread_switch(next); ptrauth_thread_switch_user(next); + permission_overlay_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case -- 2.25.1