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Wed, 11 Oct 2023 04:17:26 -0700 From: Kartik To: , , , , , , , , , , , , , , , , , Subject: [PATCH v4 7/8] soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234 Date: Wed, 11 Oct 2023 15:04:11 +0530 Message-ID: <20231011093412.7994-8-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011093412.7994-1-kkartik@nvidia.com> References: <20231011093412.7994-1-kkartik@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CY8PR12MB7196:EE_ X-MS-Office365-Filtering-Correlation-Id: ff9195ea-e6e5-4f8f-5a22-08dbca4bb08a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +SlSDC78sPwuULbX+Vy+bZs01tXAnTztfuFk674aIQm83CAqST7FY4zx1H9yt1O4Vzh5MepWNi0sAa4TAUSXC04Xog61kqTcXM/RCojJc1xJ9IO3cwxmgQS0RlQ0pLsn5/VrPa1QoAv+fCSQOqDmRKKx2iFOY+1dVRySG8W+CV+TlPHOqZ1leh9R/giBGappdOY453NsVuw6zeZ9ZpYHNSRLqOi57z5AyoiepUD9SLdGl5mVIEgmgkBHcc5kFdfnIa2yxi0DyXVC6QzWKhwLA5Xx+jZsKEs4er8wE0TljHN0r4HI4r14i2N7XB4fJG3gmVUoqa+PAc5xKC3DynUNhwUFhlhMEjMiQ3YavhqmAaAD3BPUGbJ6rCcVFVwJZ696aE8+b7P92U3aOPM0yC6+gr1W+UszLVl6syxQaiRDzTWjBE0cGgIyOH3ODbu5jNBR4noD0/xKTQJZDsWRNJQ5bdsHrsmrm+SgFOwSdIcpBmihjU2LcuqJJyshPy5Wc/95UHdmUlhZVO/rcjR0iXcAb20/KN6Hgr1SMzCZVoZ3DSX2t54kRynnGPxx5zVc4fCaqTxCk0BS6vyL5A/24g4s68yiTp2Cr9l/F4MVjVG+hpfzuw2t+FT4nVuVaXQLQu8uVgOFlbf5Uha/p3DaRksauorLZTMi9NWr6IPOEs0RYnEnWOtim5E0H5hLBOFqaG7PGlci5OUT/kPkQPbRDQ1Mstpl3zr1RreyliFt9qOWHy+XGshZ6fH+7nwBQTzzdZvBMWZ//aAfE9ZOatsN05if7on51B+pVRy9ogLbooCH+qOjIX3YAOv6jdeAeX628MbI X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(376002)(346002)(396003)(230922051799003)(64100799003)(1800799009)(186009)(451199024)(82310400011)(40470700004)(46966006)(36840700001)(40460700003)(1076003)(478600001)(6666004)(2616005)(426003)(47076005)(26005)(2906002)(70586007)(7416002)(83380400001)(70206006)(5660300002)(316002)(110136005)(336012)(8936002)(41300700001)(8676002)(82740400003)(86362001)(921005)(356005)(36860700001)(7636003)(36756003)(40480700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2023 11:17:43.5022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff9195ea-e6e5-4f8f-5a22-08dbca4bb08a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7196 X-Rspam-User: X-Stat-Signature: mi5ksng93ikyqwnptnre5anskxeybtgo X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: B6167120003 X-HE-Tag: 1697023066-146889 X-HE-Meta: U2FsdGVkX19ugMQdeKm0zwAeWuP/QUqQtDGx18m/xTu54qjSOj9SFmTHCkvdPAg2l9rZ4T60YSx6whyW2wX8g1wjo1NkxfTJPvngBPX3Z3XZZQ7G250J0MOX8CxscUyxYQNlfUJOgHx9xqpofLo/lPdd+92UxFqA97lmwgazHZExUSE3/orqudSG+2B6fPu3CYTu7Ix0WO52RePM4qUWnloEje8ltHoErfxluZCYbQr6N8Tr4TpZUWWQf356WX076AEO0W3ef/6awBIzGloH6Wy7ZdFpfW9dq7z+8shQIIhA+ZnEBiQVpWGins9VhQUX5t5bq0rp+IyejHLCSv3Nxx70WILZs81IFr8dsiI7wGoNKq1MrWMASMkbRNVQOCfvv/nXKMBC93TUPrwjozQOo+LTururBD4AmQ+U3k0KKog1WIdgy1ZlqFR8zyVsM/bmlFWPNN6Oz//P3wDs7dN1BkRVF6MkejEDxrkapmx0t6YkEG2VXtibgSK+S33OzuCc8HvsVoryezo4tw7EXpz9AT1qRRMdklVgy1VREu7gNZpnjKL46TpxT9kHuAL4nQahls/NHf64Owj4W8KeV0aXVDVA947gXsxf0K0priUQ1w3L8zn/K8cCsveYhtuVnaJb+Mi/OqprJGWdo0Tqv4db9fWAHyRNgUIIcgdByprmGvJUyg0fFEOo7D0NkTw/ri4FFDEwrU8Pu1hRnMt2C3L941QtL2qSbmCc+zvnpKdkmTDG5qSOogQbV1Ukupicq8MIU9A7k7gCSeu5WXgqutFtzSmsien/9QHRyKBd4RkttInWT6dKD5BofUDOLgcAhjekosI5Z+JJswBDezu2o/4Rzp/hJY3ktxakBk9WkIGpCwODQx6cK1Nho44lBzBBYtjD8mw5ZdanmhQXgdR+zfjJ5WgdUHxkYMF/K7lvFGeUEUxaxPIBPOY+2xInmTkVdOCR/J91iMvuhOY9wDZHdSL MIaKonc7 ZplSOBoWMxoUIb+Qml+zahn8iNhGgq6mTfBBmiTVS7GFDtQg0G+Hrr+UvEhp94tmLM1nX1+/EzhNlwbWleWbveOoZG8qfoEKsUt2JQS25OD9Wfza+efQytErxR/TGL/bsgjP2Ae1wrVItuHNA7rVt90PUrC5gtBvZQDdxsDADJRwUr6/Bp80f/fEQ9ECJ6QNWLLFpmcsX9suPuV36HbM5GPKXL784TkwLK5Xij8m2W3jdetLRK8LnRFFSzbgAg/OIeZXnANKXkO0ETqGqstDruhLpreDUbpEGhKRyW/TbCi5rzIwix/121H2Y3DG6152WnQ44Zb3CvK7H0HjjxJsN8Zdvp6i/M2+wYF3V25EQknptN92ihT38qL7nnWAzs1xFgUc0w0evpGb7oyI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add ACPI support for Tegra194 & Tegra243 SoC's. This requires following modifications to the probe when ACPI boot is used: - Initialize soc data. - Add nvmem lookups. - Register soc device. - use devm_clk_get_optional() instead of devm_clk_get() to get fuse->clk, as fuse clocks are not required when using ACPI boot. Also, drop '__init' keyword for tegra_soc_device_register() as this is also used by tegra_fuse_probe() and use dev_err_probe() wherever applicable. Signed-off-by: Kartik --- v3 -> v4: * Use dev_fwnode() to dereference the fwnode. * Add MODULE_DEVICE_TABLE for tegra_fuse_acpi_match. * Moved tegra_fuse_acpi_match above tegra_fuse_driver i.e., close to the user of tegra_fuse_acpi_match. * Moved the improvements made to fuse clk/rst get error handling to separate patch. * Moved ACPI related initialization after fuse->base is initialized in tegra_fuse_probe(), as this triggers a warning in tegra_fuse_read_early() which is called from fuse->soc->init(). v2 -> v3: * Updated commit message to specify changes related to inclusion of dev_err_probe(). v1 -> v2: * Updated ACPI ID table 'tegra_fuse_acpi_match'. * Removed ',' after "{ /* sentinel */ }" in 'tegra_fuse_acpi_match'. * Using same probe for ACPI and device-tree boot. * Added code for required initialization when ACPI boot is used. * Make clocks optional for ACPI. * Use dev_err_probe() wherever applicable. * Check if clock has been initialized only when device-tree boot is used. --- drivers/soc/tegra/fuse/fuse-tegra.c | 50 +++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 2ac9e7a03d05..167a6fe6c43d 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -3,11 +3,13 @@ * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include #include #include +#include #include #include #include @@ -155,6 +157,37 @@ static int tegra_fuse_probe(struct platform_device *pdev) return PTR_ERR(fuse->base); fuse->phys = res->start; + /* Initialize the soc data and lookups if using ACPI boot. */ + if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) { + u8 chip; + + tegra_acpi_init_apbmisc(); + + chip = tegra_get_chip_id(); + switch (chip) { +#if defined(CONFIG_ARCH_TEGRA_194_SOC) + case TEGRA194: + fuse->soc = &tegra194_fuse_soc; + break; +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + case TEGRA234: + fuse->soc = &tegra234_fuse_soc; + break; +#endif + default: + return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); + } + + fuse->soc->init(fuse); + tegra_fuse_print_sku_info(&tegra_sku_info); + tegra_soc_device_register(); + + err = tegra_fuse_add_lookups(fuse); + if (err) + return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n"); + } + fuse->clk = devm_clk_get(&pdev->dev, "fuse"); if (IS_ERR(fuse->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); @@ -278,10 +311,17 @@ static const struct dev_pm_ops tegra_fuse_pm = { SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) }; +static const struct acpi_device_id tegra_fuse_acpi_match[] = { + { "NVDA200F" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match); + static struct platform_driver tegra_fuse_driver = { .driver = { .name = "tegra-fuse", .of_match_table = tegra_fuse_match, + .acpi_match_table = ACPI_PTR(tegra_fuse_acpi_match), .pm = &tegra_fuse_pm, .suppress_bind_attrs = true, }, @@ -303,7 +343,13 @@ u32 __init tegra_fuse_read_early(unsigned int offset) int tegra_fuse_readl(unsigned long offset, u32 *value) { - if (!fuse->read || !fuse->clk) + /* + * Wait for fuse->clk to be initialized if device-tree boot is used. + */ + if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) + return -EPROBE_DEFER; + + if (!fuse->read) return -EPROBE_DEFER; if (IS_ERR(fuse->clk)) @@ -386,7 +432,7 @@ const struct attribute_group tegra194_soc_attr_group = { }; #endif -struct device * __init tegra_soc_device_register(void) +struct device *tegra_soc_device_register(void) { struct soc_device_attribute *attr; struct soc_device *dev; -- 2.34.1