From: kernel test robot <lkp@intel.com>
To: Samuel Holland <samuel@sholland.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-riscv@lists.infradead.org
Cc: oe-kbuild-all@lists.linux.dev, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel@sholland.org>
Subject: Re: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
Date: Tue, 12 Sep 2023 10:03:23 +0800 [thread overview]
Message-ID: <202309120901.kQtGm3L4-lkp@intel.com> (raw)
In-Reply-To: <20230909201727.10909-8-samuel@sholland.org>
Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.6-rc1 next-20230911]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/riscv-Apply-SiFive-CIP-1200-workaround-to-single-ASID-sfence-vma/20230910-042028
base: linus/master
patch link: https://lore.kernel.org/r/20230909201727.10909-8-samuel%40sholland.org
patch subject: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
config: riscv-nommu_k210_sdcard_defconfig (https://download.01.org/0day-ci/archive/20230912/202309120901.kQtGm3L4-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230912/202309120901.kQtGm3L4-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309120901.kQtGm3L4-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from arch/riscv/include/asm/pgtable.h:117,
from include/linux/pgtable.h:6,
from include/linux/mm.h:29,
from arch/riscv/kernel/asm-offsets.c:10:
arch/riscv/include/asm/tlbflush.h: In function 'flush_tlb_kernel_range':
>> arch/riscv/include/asm/tlbflush.h:60:9: error: implicit declaration of function 'flush_tlb_all' [-Werror=implicit-function-declaration]
60 | flush_tlb_all();
| ^~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[3]: *** [scripts/Makefile.build:116: arch/riscv/kernel/asm-offsets.s] Error 1
make[3]: Target 'prepare' not remade because of errors.
make[2]: *** [Makefile:1202: prepare0] Error 2
make[2]: Target 'prepare' not remade because of errors.
make[1]: *** [Makefile:234: __sub-make] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:234: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.
vim +/flush_tlb_all +60 arch/riscv/include/asm/tlbflush.h
fab957c11efe2f Palmer Dabbelt 2017-07-10 55
fab957c11efe2f Palmer Dabbelt 2017-07-10 56 /* Flush a range of kernel pages */
fab957c11efe2f Palmer Dabbelt 2017-07-10 57 static inline void flush_tlb_kernel_range(unsigned long start,
fab957c11efe2f Palmer Dabbelt 2017-07-10 58 unsigned long end)
fab957c11efe2f Palmer Dabbelt 2017-07-10 59 {
fab957c11efe2f Palmer Dabbelt 2017-07-10 @60 flush_tlb_all();
fab957c11efe2f Palmer Dabbelt 2017-07-10 61 }
fab957c11efe2f Palmer Dabbelt 2017-07-10 62
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
prev parent reply other threads:[~2023-09-12 2:04 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-09 20:16 [PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-09-09 20:16 ` [PATCH 1/7] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-09-09 20:16 ` [PATCH 2/7] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-09-09 20:16 ` [PATCH 3/7] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-09-09 20:16 ` [PATCH 4/7] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-09-09 20:16 ` [PATCH 5/7] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-09-09 20:16 ` [PATCH 6/7] riscv: mm: Always flush a single MM context by ASID Samuel Holland
2023-09-10 19:46 ` Conor Dooley
2023-10-26 15:53 ` Palmer Dabbelt
2023-09-09 20:16 ` [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code Samuel Holland
2023-09-09 23:02 ` kernel test robot
2023-09-11 22:08 ` kernel test robot
2023-09-12 2:03 ` kernel test robot [this message]
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