From: Samuel Holland <samuel@sholland.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-riscv@lists.infradead.org
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org,
Samuel Holland <samuel@sholland.org>
Subject: [PATCH 4/7] riscv: mm: Make asid_bits a local variable
Date: Sat, 9 Sep 2023 15:16:32 -0500 [thread overview]
Message-ID: <20230909201727.10909-5-samuel@sholland.org> (raw)
In-Reply-To: <20230909201727.10909-1-samuel@sholland.org>
This variable is only used inside asids_init().
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/riscv/mm/context.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index b5170ac1b742..43a8bc2d5af4 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -20,7 +20,6 @@
DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
-static unsigned long asid_bits;
static unsigned long num_asids;
static atomic_long_t current_version;
@@ -226,7 +225,7 @@ static inline void set_mm(struct mm_struct *prev,
static int __init asids_init(void)
{
- unsigned long old;
+ unsigned long asid_bits, old;
/* Figure-out number of ASID bits in HW */
old = csr_read(CSR_SATP);
--
2.41.0
next prev parent reply other threads:[~2023-09-09 20:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-09 20:16 [PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-09-09 20:16 ` [PATCH 1/7] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-09-09 20:16 ` [PATCH 2/7] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-09-09 20:16 ` [PATCH 3/7] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-09-09 20:16 ` Samuel Holland [this message]
2023-09-09 20:16 ` [PATCH 5/7] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-09-09 20:16 ` [PATCH 6/7] riscv: mm: Always flush a single MM context by ASID Samuel Holland
2023-09-10 19:46 ` Conor Dooley
2023-10-26 15:53 ` Palmer Dabbelt
2023-09-09 20:16 ` [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code Samuel Holland
2023-09-09 23:02 ` kernel test robot
2023-09-11 22:08 ` kernel test robot
2023-09-12 2:03 ` kernel test robot
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