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From: Conor Dooley <conor.dooley@microchip.com>
To: kernel test robot <lkp@intel.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<oe-kbuild-all@lists.linux.dev>,
	Linux Memory Management List <linux-mm@kvack.org>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
Date: Thu, 31 Aug 2023 10:16:42 +0100	[thread overview]
Message-ID: <20230831-congested-monument-44ddb496204d@wendy> (raw)
In-Reply-To: <202308311610.ec6bm2G8-lkp@intel.com>

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On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> head:   a47fc304d2b678db1a5d760a7d644dac9b067752
> commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> compiler: riscv64-linux-gcc (GCC) 13.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> 
> All error/warnings (new ones prefixed by >>):
> 
>    arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
>       29 |         struct sbiret ret;
>          |                       ^~~
> >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
>       35 |         ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
>          |               ^~~~~~~~~
> >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
>       29 |         struct sbiret ret;
>          |                       ^~~
>    cc1: some warnings being treated as errors
> 
> 
> vim +29 arch/riscv/errata/andes/errata.c
> 
>     26	
>     27	static long ax45mp_iocp_sw_workaround(void)
>     28	{
>   > 29		struct sbiret ret;
>     30	
>     31		/*
>     32		 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
>     33		 * cache is controllable only then CMO will be applied to the platform.
>     34		 */
>   > 35		ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
>     36				0, 0, 0, 0, 0, 0);
>     37	
>     38		return ret.error ? 0 : ret.value;
>     39	}
>     40	

Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
to grow a dependency on RISCV_SBI.

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  reply	other threads:[~2023-08-31  9:17 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-31  8:52 kernel test robot
2023-08-31  9:16 ` Conor Dooley [this message]
2023-08-31 11:22   ` [WARNING: ATTACHMENT UNSCANNED]Re: " Lad, Prabhakar
2023-08-31 11:33     ` Conor Dooley
2023-08-31 11:53       ` Lad, Prabhakar
2023-08-31 12:01         ` Geert Uytterhoeven
2023-08-31 13:01           ` Lad, Prabhakar
2023-08-31 13:24             ` Geert Uytterhoeven
2023-08-31 14:59               ` Lad, Prabhakar
2023-08-31 16:36                 ` Conor Dooley
2023-09-01  8:34                   ` Lad, Prabhakar

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