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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT066.mail.protection.outlook.com (10.13.175.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6319.27 via Frontend Transport; Fri, 21 Apr 2023 15:37:31 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 21 Apr 2023 10:37:30 -0500 Date: Fri, 21 Apr 2023 10:35:14 -0500 From: Michael Roth To: Sean Christopherson CC: Atish Patra , , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , , Dylan Reid , , Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , , , , , Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Subject: Re: [RFC 00/48] RISC-V CoVE support Message-ID: <20230421153514.tpqzvdu7zt7pe7hs@amd.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2023 15:37:31.3816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a66fb1eb-af32-4c61-03c0-08db427e5232 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6111 X-Stat-Signature: 1n36apwoskhe3tm6kcyu87bqa7k6rj4e X-Rspam-User: X-Rspamd-Queue-Id: 4C1091C0004 X-Rspamd-Server: rspam06 X-HE-Tag: 1682091455-744140 X-HE-Meta: U2FsdGVkX1/0tcaCBtIfZoC88bVIDlYJ2I5DgayRdFvVveQeDLNYg4+c4088DmX6VWxNCMyZawMNcmVn+QZTcy3Bz6ZoMhYDf5WUgdEiC57VbcGTwBo0fFf6J/ej0KyafIDmemG6TcCs+ZBDFJDeYpmqRDdgYxfIESkdmStVdqZC9ny9efxKAj3l8pjLat7vPvBvoB0dbkzpTvHBNFMDKPEfXPyabFdTfmi3p2v3w83irokPdHEnlde6Mswmrs0dA1vC+hLH4kikIgzlJZynSH1h4IdT5iCyxjg1CZWvEapyWlzqJOAsDU3pPductxIbvv5USCe/Mhu60arzsLPpvlizp09dzrlL/osO3XNlU2h1X+gKIGIFimnLML2B+CCE5rO0vs0lyYPp14S72547OOjQw6C7pdDddjyI6tdgMoHbkgEmf7lpqyvrJ6gqnUFyYQX4cFlt+qlRpXuQsZENudoeW5COBuAE0J2QGtYVygrLWgH4iOSYebsZgKeYU+z2WhAeWcCClAj+yml5j3HVK+z4fFJlyctas2eOCccuU2KkH4zRxTYufnQc3SgT5arh57Yif0MeU9gVC/Bjs5EX3oAxYVAix00E6ZhQyPcN9xXwsOgzSqPLUzlyTFp+cnSMWyQ8aT5elVy6wAch93OZJpH38qjIVDdcEPFAnbPBPFzfwxwG/EPFz7R+eX5qSPHNhkDtSMa24vsHS/WexHLJ46DnGPw6zqTR4ImNpUthj96E5ZGTCtAxCGU1qvHDUp1LkALQ8H1373j2poGveIuh9uxbI8cHEgGZVY4CSaB9m80JXsO5IWoM8/yVWw0UYQCfhMIh6aM3A84K1f+XguCiNgenQJxivS61T9Cj5yRaa9bL29sl1r36M9ztHr3JFge5ZHeZLnwJFwNd6k8Ms6E+v8O2Aqt8Wv8ojq8VUdxxauL01pt2vcb8VD6FMgo7oXHNhYbWX57uEoDpZMKqxh6 qIdK1Klq 2M55iN/xRzkdJMUHCFNiuMDwmhP5DnenaVvdds9dOi8DEUGVHHhxwJo0Gwh0UkwbX+6D7XmQArohZov3JMlv/9kz3hSovsLgHwb8MFx520dr7yf2vtQ/roENJe1yMW/5YdlNOMF321GzXJrhXCpLUAvMTAfJ73SDmMG5ysZF24DX07uk9R8AZM6htTmlHmUm5CqfFjD5YsVGuHPVJRkGnyTYyvaCAw1oA6GS/OS4/pZ3z8ckNaZY8szYGQHPQ06FEKTaTpSp3lGYt6uvmQR2Kqi0553P81dBDj2FXSogsKIVkhp8N6EJ4UvLwrloTEcHRU/gWe8lvomIhqJ2XgDXDf5UNxfuv7AXu53Vqf5Ghb3cu7VLZKmqUeTl+aj4Jr2lncDjV X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, Apr 20, 2023 at 09:30:29AM -0700, Sean Christopherson wrote: > Please, go look at restrictedmem[2] and work on building CoVE support on top of > that. If the current proposal doesn't fit CoVE's needs, then we need to know _before_ > all of that code gets merged. I agree it's preferable to know beforehand to avoid potential maintainability quagmires bringing additional architectures onboard, and that it probably makes sense here to get that early input. But as a general statement, it's not necessarily a *requirement*. I worry that if we commit to such a policy that by the time restrictedmem gets close to merge, yet another architecture/use-case will come along that delays things further for architectures that already have hardware in the field. Not saying that's the case here, but just in general I think it's worth keeping the option open on iterating on a partial solution vs. trying to address everything on the first shot, depending on how the timing works out. Thanks, Mike > > [1] https://lore.kernel.org/linux-mm/20200522125214.31348-1-kirill.shutemov@linux.intel.com > [2] https://lkml.kernel.org/r/20221202061347.1070246-1-chao.p.peng%40linux.intel.com > > > arch/riscv/Kbuild | 2 + > > arch/riscv/Kconfig | 27 + > > arch/riscv/cove/Makefile | 2 + > > arch/riscv/cove/core.c | 40 + > > arch/riscv/cove/cove_guest_sbi.c | 109 +++ > > arch/riscv/include/asm/cove.h | 27 + > > arch/riscv/include/asm/covg_sbi.h | 38 + > > arch/riscv/include/asm/csr.h | 2 + > > arch/riscv/include/asm/kvm_cove.h | 206 +++++ > > arch/riscv/include/asm/kvm_cove_sbi.h | 101 +++ > > arch/riscv/include/asm/kvm_host.h | 10 +- > > arch/riscv/include/asm/kvm_vcpu_sbi.h | 3 + > > arch/riscv/include/asm/mem_encrypt.h | 26 + > > arch/riscv/include/asm/sbi.h | 107 +++ > > arch/riscv/include/uapi/asm/kvm.h | 17 + > > arch/riscv/kernel/irq.c | 12 + > > arch/riscv/kernel/setup.c | 2 + > > arch/riscv/kvm/Makefile | 1 + > > arch/riscv/kvm/aia.c | 101 ++- > > arch/riscv/kvm/aia_device.c | 41 +- > > arch/riscv/kvm/aia_imsic.c | 127 ++- > > arch/riscv/kvm/cove.c | 1005 +++++++++++++++++++++++ > > arch/riscv/kvm/cove_sbi.c | 490 +++++++++++ > > arch/riscv/kvm/main.c | 30 +- > > arch/riscv/kvm/mmu.c | 45 +- > > arch/riscv/kvm/tlb.c | 11 +- > > arch/riscv/kvm/vcpu.c | 69 +- > > arch/riscv/kvm/vcpu_exit.c | 34 +- > > arch/riscv/kvm/vcpu_insn.c | 115 ++- > > arch/riscv/kvm/vcpu_sbi.c | 16 + > > arch/riscv/kvm/vcpu_sbi_covg.c | 232 ++++++ > > arch/riscv/kvm/vcpu_timer.c | 26 +- > > arch/riscv/kvm/vm.c | 34 +- > > arch/riscv/kvm/vmid.c | 17 +- > > arch/riscv/mm/Makefile | 3 + > > arch/riscv/mm/init.c | 17 +- > > arch/riscv/mm/ioremap.c | 45 + > > arch/riscv/mm/mem_encrypt.c | 61 ++ > > drivers/tty/hvc/hvc_riscv_sbi.c | 5 + > > drivers/tty/serial/earlycon-riscv-sbi.c | 51 +- > > include/uapi/linux/kvm.h | 8 + > > mm/vmalloc.c | 16 + > > 42 files changed, 3222 insertions(+), 109 deletions(-) > > create mode 100644 arch/riscv/cove/Makefile > > create mode 100644 arch/riscv/cove/core.c > > create mode 100644 arch/riscv/cove/cove_guest_sbi.c > > create mode 100644 arch/riscv/include/asm/cove.h > > create mode 100644 arch/riscv/include/asm/covg_sbi.h > > create mode 100644 arch/riscv/include/asm/kvm_cove.h > > create mode 100644 arch/riscv/include/asm/kvm_cove_sbi.h > > create mode 100644 arch/riscv/include/asm/mem_encrypt.h > > create mode 100644 arch/riscv/kvm/cove.c > > create mode 100644 arch/riscv/kvm/cove_sbi.c > > create mode 100644 arch/riscv/kvm/vcpu_sbi_covg.c > > create mode 100644 arch/riscv/mm/ioremap.c > > create mode 100644 arch/riscv/mm/mem_encrypt.c > > > > -- > > 2.25.1 > > >