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Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , Linus Torvalds , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv14 03/17] x86: CPUID and CR3/CR4 flags for Linear Address Masking Date: Wed, 11 Jan 2023 15:37:22 +0300 Message-Id: <20230111123736.20025-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20230111123736.20025-1-kirill.shutemov@linux.intel.com> References: <20230111123736.20025-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 37491180009 X-Stat-Signature: 5u6ryoah3qds1cxy1ni974x4upzbabka X-HE-Tag: 1673443443-996417 X-HE-Meta: U2FsdGVkX1+hj9GuiHoHuyPqJo9kuBdacMCKNm1jQ8cSR1ME4ncC1fIRdEy0ydLJOE/55TaK8WnAb2v79citCBzAHe9XVeOKtDumE6DG87Of7/BGFiRDecUbsoHHCRdlsbfYjc/If09+USa1MElAsN7CTP/27XWBdx7XmMOjnmM5zHn5N34VYcl8hmOevrCEBwHU/qt++TrCmZvHcIEnw9mOZq4PSyd6eqE981A8euvfLNftYcplrw5UlUHN3v3W2bTAby+45z4DqHp3twUyKj1Eu+HinZUaDhn28Td9JyMAxwJ1+3bBqYGTu473AQQI03FPFuPesYh62eQOA7Osr/4m5bdjYtAkEtg+dx1GoVrVRJUvpRL+nMWi1ldsRBHvHMepOmIDrbBt+3Z/KOTQZy6mD0mPh6ZOdn1rtAYoBVe6ggu8bEIF0EySqnn871KeyJO8osN1mlSCg3OJuXR6LOHEr99D7ENdp8/H39iPs80ihLKVTSGj/OUhNJTcEmdO/b+ToQ6Csr6TwxbmjOpZcIrcF5c2SWf0OyBEETvHlovujbgKKC4VpHZtsDrZTNuCzledpBt58fOx2PK5OlJRLFxTnXea9dGl74AE9V5JJY/JMB5WidwoXDc61vn1QUiqUIospFjkvQDQgjxPiN6tiwQYkZIc8pRXuDcVRXlVqrNZnCgGleDTnuWgK0771LGOCyuyAcNG/gRVLgr6ksc1ba/QokgYW/rSYevu0Y0yGyf6gfrWlxieXNDITbYGLEMEjdazg9M/u4b3JrkMom+OcJ447ucm+5mDk8ZlzXE4w7ZJpaRXPvB1aevGodj/k4wdnjvajqRYy4bRNytcRn1NsYjSETt5eurXZDqnoL6qVlwduFjJTL55sOj1F5yznNR+fgGIr7iVwrNzhfkuJWQ5Mx5EWbx3Pn/V3AhsD5yLQoto3DDIRCOl5Iawk5+poQjPOQ3DfPkNdrU= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Enumerate Linear Address Masking and provide defines for CR3 and CR4 flags. The new CONFIG_ADDRESS_MASKING option enables the feature support in kernel. Signed-off-by: Kirill A. Shutemov Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) Tested-by: Alexander Potapenko --- arch/x86/Kconfig | 11 +++++++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/processor-flags.h | 2 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++ 4 files changed, 20 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3604074a878b..211869aa618d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2290,6 +2290,17 @@ config RANDOMIZE_MEMORY_PHYSICAL_PADDING If unsure, leave at the default value. +config ADDRESS_MASKING + bool "Linear Address Masking support" + depends on X86_64 + help + Linear Address Masking (LAM) modifies the checking that is applied + to 64-bit linear addresses, allowing software to use of the + untranslated address bits for metadata. + + The capability can be used for efficient address sanitizers (ASAN) + implementation and for optimizations in JITs. + config HOTPLUG_CPU def_bool y depends on SMP diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..bc662c80b99d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -314,6 +314,7 @@ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index a7f3d9100adb..d8cccadc83a6 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -28,6 +28,8 @@ * On systems with SME, one bit (in a variable position!) is stolen to indicate * that the top-level paging structure is encrypted. * + * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. + * * All of the remaining bits indicate the physical address of the top-level * paging structure. * diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..d898432947ff 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -82,6 +82,10 @@ #define X86_CR3_PCID_BITS 12 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) +#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits masked */ +#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT) +#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits masked */ +#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT) #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) @@ -132,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ +#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) /* * x86-64 Task Priority Register, CR8 -- 2.38.2