tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 4d48f589d294ddc5e01d3b0dc7cecc55324c05ca commit: c888183b21f36a247bb166ca9365705611bea847 [637/2652] wifi: rtl8xxxu: Support new chip RTL8188FU config: i386-allyesconfig compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=c888183b21f36a247bb166ca9365705611bea847 git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout c888183b21f36a247bb166ca9365705611bea847 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/ drivers/net/wireless/ath/ath11k/ drivers/net/wireless/realtek/rtl8xxxu/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All warnings (new ones prefixed by >>): >> drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c:432:7: warning: variable 'hw_ctrl_s1' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] if (hw_ctrl) { ^~~~~~~ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c:440:7: note: uninitialized use occurs here if (hw_ctrl_s1 || sw_ctrl_s1) { ^~~~~~~~~~ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c:432:3: note: remove the 'if' if its condition is always true if (hw_ctrl) { ^~~~~~~~~~~~~ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c:415:45: note: initialize the variable 'hw_ctrl_s1' to silence this warning bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1, sw_ctrl_s1; ^ = 0 1 warning generated. vim +432 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c 384 385 /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ 386 static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) 387 { 388 static const u32 frequencies[14 + 1] = { 389 [5] = 0xFCCD, 390 [6] = 0xFC4D, 391 [7] = 0xFFCD, 392 [8] = 0xFF4D, 393 [11] = 0xFDCD, 394 [13] = 0xFCCD, 395 [14] = 0xFF9A 396 }; 397 398 static const u32 reg_d40[14 + 1] = { 399 [5] = 0x06000000, 400 [6] = 0x00000600, 401 [13] = 0x06000000 402 }; 403 404 static const u32 reg_d44[14 + 1] = { 405 [11] = 0x04000000 406 }; 407 408 static const u32 reg_d4c[14 + 1] = { 409 [7] = 0x06000000, 410 [8] = 0x00000380, 411 [14] = 0x00180000 412 }; 413 414 const u8 threshold = 0x16; 415 bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1, sw_ctrl_s1; 416 u32 val32, initial_gain, reg948; 417 418 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 419 val32 |= GENMASK(28, 24); 420 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 421 422 /* enable notch filter */ 423 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 424 val32 |= BIT(9); 425 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 426 427 if (channel <= 14 && frequencies[channel] > 0) { 428 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 429 hw_ctrl = reg948 & BIT(6); 430 sw_ctrl = !hw_ctrl; 431 > 432 if (hw_ctrl) { 433 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 434 val32 &= GENMASK(5, 3); 435 hw_ctrl_s1 = val32 == BIT(3); 436 } else if (sw_ctrl) { 437 sw_ctrl_s1 = !(reg948 & BIT(9)); 438 } 439 440 if (hw_ctrl_s1 || sw_ctrl_s1) { 441 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 442 443 /* Disable CCK block */ 444 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 445 val32 &= ~FPGA_RF_MODE_CCK; 446 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 447 448 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; 449 val32 |= 0x30; 450 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 451 452 /* disable 3-wire */ 453 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 454 455 /* Setup PSD */ 456 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 457 458 /* Start PSD */ 459 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); 460 461 msleep(30); 462 463 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; 464 465 /* turn off PSD */ 466 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 467 468 /* enable 3-wire */ 469 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); 470 471 /* Enable CCK block */ 472 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 473 val32 |= FPGA_RF_MODE_CCK; 474 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 475 476 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); 477 478 if (do_notch) { 479 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); 480 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); 481 rtl8xxxu_write32(priv, 0xd48, 0x0); 482 rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); 483 484 /* enable CSI mask */ 485 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 486 val32 |= BIT(28); 487 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 488 489 return; 490 } 491 } 492 } 493 494 /* disable CSI mask function */ 495 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 496 val32 &= ~BIT(28); 497 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 498 } 499 -- 0-DAY CI Kernel Test Service https://01.org/lkp