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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id y135-20020a62ce8d000000b0055f811897d8sm5403435pfg.73.2022.10.03.10.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 10:48:30 -0700 (PDT) Date: Mon, 3 Oct 2022 10:48:29 -0700 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Weijiang Yang , "Kirill A . Shutemov" , joao.moreira@intel.com, John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com Subject: Re: [PATCH v2 06/39] x86/fpu: Add helper for modifying xstate Message-ID: <202210031045.419F7DB396@keescook> References: <20220929222936.14584-1-rick.p.edgecombe@intel.com> <20220929222936.14584-7-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220929222936.14584-7-rick.p.edgecombe@intel.com> ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1664819311; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=8KcKcFPOC4l2l7q42vPtJKHACw1c6U1nHGwLuGCBrtI=; b=OpEBuawL1l6c8sQf4bokgqLI1I+PUku6fTOfRxj5Y5RZ6K4M9r2kDo9SEljHWMG15b++qV KZDLdNKeo8wBVbj2Y3OeA1hJSwkX3TCjnMMrji+VjgvOkdtqClG+g7jD3wFZTUrHVUrgjj kdOH/UJAQktKUa0glF/yEJTWe3Siv7U= ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=pass header.d=chromium.org header.s=google header.b=eCxjnyQO; dmarc=pass (policy=none) header.from=chromium.org; spf=pass (imf02.hostedemail.com: domain of keescook@chromium.org designates 209.85.215.177 as permitted sender) smtp.mailfrom=keescook@chromium.org ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1664819311; a=rsa-sha256; cv=none; b=tKiY8PqoVC6ioPeLtD5JwJeilzGc/3bqsjcw6Lhb/cB6HRtkHVjR1UdhbeIJO5pDfP0zaw pULrc15AG1S5c+Yhe43xIn9oO8/Kqmxhwkvh+Ppz+SZX0Y0lAK/A+I+A+ITXRHvrr/nHtR IIOD2QLCKxXfz4feJ8E2XlmYNVulFuQ= X-Stat-Signature: soktfihpkf5jcj76umfn9h7ie4bn84w7 X-Rspam-User: X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: BE94380017 Authentication-Results: imf02.hostedemail.com; dkim=pass header.d=chromium.org header.s=google header.b=eCxjnyQO; dmarc=pass (policy=none) header.from=chromium.org; spf=pass (imf02.hostedemail.com: domain of keescook@chromium.org designates 209.85.215.177 as permitted sender) smtp.mailfrom=keescook@chromium.org X-HE-Tag: 1664819311-899736 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, Sep 29, 2022 at 03:29:03PM -0700, Rick Edgecombe wrote: > Just like user xfeatures, supervisor xfeatures can be active in the > registers or present in the task FPU buffer. If the registers are > active, the registers can be modified directly. If the registers are > not active, the modification must be performed on the task FPU buffer. > > When the state is not active, the kernel could perform modifications > directly to the buffer. But in order for it to do that, it needs > to know where in the buffer the specific state it wants to modify is > located. Doing this is not robust against optimizations that compact > the FPU buffer, as each access would require computing where in the > buffer it is. > > The easiest way to modify supervisor xfeature data is to force restore > the registers and write directly to the MSRs. Often times this is just fine > anyway as the registers need to be restored before returning to userspace. > Do this for now, leaving buffer writing optimizations for the future. Just for my own clarity, does this mean lock/load _needs_ to happen before MSR access, or is it just a convenient place to do it? From later patches it seems it's a requirement during MSR access, which might be a good idea to detail here. It answers the question "when is this function needed?" > > Add a new function fpregs_lock_and_load() that can simultaneously call > fpregs_lock() and do this restore. Also perform some extra sanity > checks in this function since this will be used in non-fpu focused code. Nit: this is called "fpu_lock_and_load" in the patch itself. > > Suggested-by: Thomas Gleixner > Signed-off-by: Rick Edgecombe Reviewed-by: Kees Cook -- Kees Cook