From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Ashok Raj <ashok.raj@intel.com>
Cc: Jason Gunthorpe <jgg@nvidia.com>,
Dave Hansen <dave.hansen@intel.com>,
Jacob Pan <jacob.jun.pan@intel.com>,
"Kirill A. Shutemov" <kirill@shutemov.name>,
Ashok Raj <ashok_raj@linux.intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
x86@kernel.org, Kostya Serebryany <kcc@google.com>,
Andrey Ryabinin <ryabinin.a.a@gmail.com>,
Andrey Konovalov <andreyknvl@gmail.com>,
Alexander Potapenko <glider@google.com>,
Taras Madan <tarasmadan@google.com>,
Dmitry Vyukov <dvyukov@google.com>,
"H . J . Lu" <hjl.tools@gmail.com>,
Andi Kleen <ak@linux.intel.com>,
Rick Edgecombe <rick.p.edgecombe@intel.com>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCHv8 00/11] Linear Address Masking enabling
Date: Fri, 23 Sep 2022 12:38:26 +0300 [thread overview]
Message-ID: <20220923093826.kjad4qe3clwybeh6@box.shutemov.name> (raw)
In-Reply-To: <Yy1D0dLdqTr7ya71@a4bf019067fa.jf.intel.com>
On Thu, Sep 22, 2022 at 10:27:45PM -0700, Ashok Raj wrote:
> On Fri, Sep 23, 2022 at 03:42:39AM +0300, Kirill A. Shutemov wrote:
> > On Wed, Sep 21, 2022 at 03:11:34PM -0300, Jason Gunthorpe wrote:
> > > On Wed, Sep 21, 2022 at 10:11:46AM -0700, Dave Hansen wrote:
> > >
> > > > Are you saying that any device compatibility with an mm is solely
> > > > determined by the IOMMU in play, so the IOMMU code should host the mm
> > > > compatibility checks?
> > >
> > > Yes, exactly. Only the HW entity that walks the page tables needs to
> > > understand their parsing rules and in this case that is only the IOMMU
> > > block.
> >
> > But device has to know what bits of the virtual address are significant to
> > handle device TLB lookup/store correctly, no?
>
> For a device that also cares about tagging, yes. But in the current
> world we don't have such devices. IOMMU only knows about the shared cr3
> we placed in the PASID table entries to walk page-tables. I hope the
> page-tables don't factor the meta-data bits correct?
Correct. Page tables contain only physical addresses, so they have no
exposure to tags in the virtual addresses.
> So I would assume an untagged pointer should just be fine for the IOMMU
> to walk. IOMMU currently wants canonical addresses for VA.
Right. But it means that LAM compatibility can be block on two layers:
IOMMU and device. IOMMU is not the only HW entity that has to be aware of
tagged pointers.
So where to put compatibility check that can cover both device and IOMMU,
considering that in the future they can get aware about tagged pointers?
--
Kiryl Shutsemau / Kirill A. Shutemov
next prev parent reply other threads:[~2022-09-23 9:38 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-30 1:00 Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 01/11] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 02/11] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 03/11] mm: Pass down mm_struct to untagged_addr() Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 04/11] x86/mm: Handle LAM on context switch Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 05/11] x86/uaccess: Provide untagged_addr() and remove tags before address check Kirill A. Shutemov
2022-08-30 1:00 ` [PATCHv8 06/11] x86/mm: Provide arch_prctl() interface for LAM Kirill A. Shutemov
2022-08-30 1:01 ` [PATCHv8 07/11] x86: Expose untagging mask in /proc/$PID/arch_status Kirill A. Shutemov
2022-08-30 1:01 ` [PATCHv8 08/11] selftests/x86/lam: Add malloc and tag-bits test cases for linear-address masking Kirill A. Shutemov
2022-08-30 1:01 ` [PATCHv8 09/11] selftests/x86/lam: Add mmap and SYSCALL " Kirill A. Shutemov
2022-09-07 3:19 ` Robert Hoo
2022-09-09 11:24 ` Zhang, Weihong
2022-08-30 1:01 ` [PATCHv8 10/11] selftests/x86/lam: Add io_uring " Kirill A. Shutemov
2022-08-30 1:01 ` [PATCHv8 11/11] selftests/x86/lam: Add inherit " Kirill A. Shutemov
2022-09-01 17:45 ` [PATCHv8 00/11] Linear Address Masking enabling Ashok Raj
2022-09-04 0:39 ` Kirill A. Shutemov
2022-09-09 16:08 ` Ashok Raj
2022-09-12 20:39 ` Jacob Pan
2022-09-12 21:41 ` Dave Hansen
2022-09-12 22:55 ` Jacob Pan
2022-09-13 0:06 ` Kirill A. Shutemov
2022-09-13 0:23 ` Ashok Raj
2022-09-12 22:49 ` Kirill A. Shutemov
2022-09-13 0:08 ` Jacob Pan
2022-09-13 0:18 ` Kirill A. Shutemov
2022-09-14 14:45 ` Kirill A. Shutemov
2022-09-14 15:11 ` Ashok Raj
2022-09-14 15:18 ` Kirill A. Shutemov
2022-09-14 15:31 ` Ashok Raj
2022-09-14 15:45 ` Kirill A. Shutemov
2022-09-14 23:51 ` Jacob Pan
2022-09-15 9:01 ` Kirill A. Shutemov
2022-09-15 17:28 ` Kirill A. Shutemov
2022-09-20 13:14 ` Jason Gunthorpe
2022-09-20 14:57 ` Ashok Raj
2022-09-20 16:06 ` Dave Hansen
2022-09-20 16:27 ` Jason Gunthorpe
2022-09-20 18:41 ` Jacob Pan
2022-09-20 18:50 ` Jason Gunthorpe
2022-09-20 20:44 ` Jacob Pan
2022-09-21 0:01 ` Jason Gunthorpe
2022-09-21 9:36 ` Tian, Kevin
2022-09-21 16:57 ` Dave Hansen
2022-09-21 17:08 ` Ashok Raj
2022-09-21 17:11 ` Dave Hansen
2022-09-21 17:29 ` Ashok Raj
2022-09-21 18:11 ` Jason Gunthorpe
2022-09-23 0:42 ` Kirill A. Shutemov
2022-09-23 5:27 ` Ashok Raj
2022-09-23 9:38 ` Kirill A. Shutemov [this message]
2022-09-23 11:46 ` Jason Gunthorpe
2022-09-23 14:18 ` Dave Hansen
2022-09-23 14:42 ` Jason Gunthorpe
2022-09-23 14:59 ` Ashok Raj
2022-09-23 15:28 ` Ashok Raj
2022-09-23 15:31 ` Dave Hansen
2022-09-23 15:44 ` Ashok Raj
2022-09-23 16:23 ` Dave Hansen
2022-09-23 16:44 ` Jason Gunthorpe
2022-09-04 1:00 ` Kirill A. Shutemov
2022-09-05 5:05 ` Bharata B Rao
2022-09-05 13:44 ` Kirill A. Shutemov
2022-09-05 14:30 ` Peter Zijlstra
2022-09-05 15:35 ` Kirill A. Shutemov
2022-09-05 15:46 ` Peter Zijlstra
2022-09-05 16:47 ` Kirill A. Shutemov
2022-09-06 8:39 ` Peter Zijlstra
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