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McKenney" , Frederic Weisbecker , Vitaly Wool , Myrtle Shah , Nick Knight , Catalin Marinas , Mark Brown , Will Deacon , Jiaxun Yang , Janosch Frank , Alexey Dobriyan , Huacai Chen , Christian Brauner , Andrew Morton , Colin Cross , Eugene Syromiatnikov , Peter Collingbourne , Barret Rhoden , Suren Baghdasaryan , Davidlohr Bueso , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Date: Wed, 21 Sep 2022 14:43:49 -0700 Message-Id: <20220921214439.1491510-7-stillson@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com> References: <20220921214439.1491510-1-stillson@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ARC-Authentication-Results: i=1; imf13.hostedemail.com; dkim=pass header.d=rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="2Zivm6A/"; dmarc=none; spf=pass (imf13.hostedemail.com: domain of stillson@rivosinc.com designates 209.85.214.178 as permitted sender) smtp.mailfrom=stillson@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1663796961; a=rsa-sha256; cv=none; b=FsWnaK5vQdlAiIhQcsrvYaHn0DYCGT6kGjKHkUNxK2r24ET4ba3233wZ5l8CQl1uq960tT tU1NGiAptw9Vsmukj7vAsL3SYjMDq2mx7ojhZ/Kqe/Xa9Y/Ix0pWMMq/0oCwR+CFd/xvuK 3SI/4UF4AScyjluTTbZI8kEUIfwLKrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1663796961; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=BvXu+QXgzcKTzY7GQZ6McuBPlZWnkV19grD1UPI3mnI=; b=5ztlJLU16ZOnWKSlP/DNVqUozhs36V+agfUKvtwMr/WQDRO81/phJvMvt4K1kWIUoSH1cl Nub2UHqQljX6Sb6kQIEinxijtgsCiihVfG6ye3lr2AU/WvCHnKCT38aCDsjMV7uN6a4lBV XEioUBnQSzMvG7iIJJs3FX6H8uYZ7i0= Authentication-Results: imf13.hostedemail.com; dkim=pass header.d=rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="2Zivm6A/"; dmarc=none; spf=pass (imf13.hostedemail.com: domain of stillson@rivosinc.com designates 209.85.214.178 as permitted sender) smtp.mailfrom=stillson@rivosinc.com X-Rspamd-Server: rspam06 X-Stat-Signature: hm7ntnouthqm4ajrsokjwz41z4mdpkos X-Rspam-User: X-Rspamd-Queue-Id: 968F82003D X-HE-Tag: 1663796961-649173 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Greentime Hu Add vector state context struct in struct thread and asm-offsets.c definitions. The vector registers will be saved in datap pointer of __riscv_v_state. It will be dynamically allocated in kernel space. It will be put right after the __riscv_v_state data structure in user space. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 17 +++++++++++++++++ arch/riscv/kernel/asm-offsets.c | 6 ++++++ 3 files changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 19eedd4af4cd..95917a2b24f9 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_state vstate; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 882547f6bd5c..6ee1ca2edfa7 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,6 +77,23 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; +struct __riscv_v_state { + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + void *datap; + /* + * In signal handler, datap will be set a correct user stack offset + * and vector registers will be copied to the address of datap + * pointer. + * + * In ptrace syscall, datap will be set to zero and the vector + * registers will be copied to the address right after this + * structure. + */ +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index df9444397908..37e3e6a8d877 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -75,6 +75,12 @@ void asm_offsets(void) OFFSET(TSK_STACK_CANARY, task_struct, stack_canary); #endif + OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart); + OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl); + OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype); + OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr); + OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap); + DEFINE(PT_SIZE, sizeof(struct pt_regs)); OFFSET(PT_EPC, pt_regs, epc); OFFSET(PT_RA, pt_regs, ra); -- 2.25.1