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Wed, 21 Sep 2022 14:47:14 -0700 (PDT) From: Chris Stillson To: Cc: Guo Ren , Greentime Hu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Anup Patel , Atish Patra , Oleg Nesterov , Guo Ren , Heinrich Schuchardt , Arnaud Pouliquen , Chris Stillson , Paolo Bonzini , Qinglin Pan , Alexandre Ghiti , Vincent Chen , Arnd Bergmann , Heiko Stuebner , Jisheng Zhang , Dao Lu , "Peter Zijlstra (Intel)" , Sunil V L , Han-Kuan Chen , Changbin Du , Li Zhengyu , Alexander Graf , Ard Biesheuvel , Tsukasa OI , Yury Norov , Frederic Weisbecker , Mark Rutland , Myrtle Shah , Vitaly Wool , Mathieu Desnoyers , Catalin Marinas , Mark Brown , Will Deacon , Heiko Carstens , Huacai Chen , Alexey Dobriyan , Janosch Frank , Christian Brauner , Evgenii Stepanov , Peter Collingbourne , Eugene Syromiatnikov , Colin Cross , Andrew Morton , Suren Baghdasaryan , Barret Rhoden , Davidlohr Bueso , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v12 04/17] riscv: Add vector feature to compile Date: Wed, 21 Sep 2022 14:43:46 -0700 Message-Id: <20220921214439.1491510-4-stillson@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com> References: <20220921214439.1491510-1-stillson@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ARC-Seal: i=1; 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dkim=pass header.d=rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=eM8rXH1Y; dmarc=none; spf=pass (imf02.hostedemail.com: domain of stillson@rivosinc.com designates 209.85.215.174 as permitted sender) smtp.mailfrom=stillson@rivosinc.com X-Rspamd-Server: rspam02 X-Rspam-User: X-HE-Tag: 1663796835-712711 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Guo Ren This patch adds a new config option which could enable assembler's vector feature. Signed-off-by: Guo Ren Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu --- arch/riscv/Kconfig | 15 +++++++++++++-- arch/riscv/Makefile | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ed66c31e4655..e294d85bfb7d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -432,7 +432,17 @@ config FPU If you don't know what to do here, say Y. -endmenu # "Platform type" +config VECTOR + bool "VECTOR support" + depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000 + default n + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + +endmenu menu "Kernel features" @@ -556,6 +566,7 @@ config CMDLINE_EXTEND cases where the provided arguments are insufficient and you don't want to or cannot modify them. + config CMDLINE_FORCE bool "Always use the default kernel command string" help @@ -648,7 +659,7 @@ config XIP_PHYS_ADDR be linked for and stored to. This address is dependent on your own flash usage. -endmenu # "Boot options" +endmenu config BUILTIN_DTB bool diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 3fa8ef336822..1ec17f3d6d09 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -50,6 +50,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_VECTOR) := $(riscv-march-y)v # Newer binutils versions default to ISA spec version 20191213 which moves some # instructions from the I extension to the Zicsr and Zifencei extensions. -- 2.25.1