tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 5b6a4bf680d61b1dd26629840f848d0df8983c62 commit: 81c0386c1376da54f05d6916936db5220df9f97d [1581/2065] regmap: mmio: Support accelerared noinc operations config: alpha-randconfig-r031-20220818 compiler: alpha-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=81c0386c1376da54f05d6916936db5220df9f97d git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout 81c0386c1376da54f05d6916936db5220df9f97d # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=alpha SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot All errors (new ones prefixed by >>): drivers/base/regmap/regmap-mmio.c: In function 'regmap_mmio_noinc_write': drivers/base/regmap/regmap-mmio.c:221:17: error: implicit declaration of function 'writesb'; did you mean 'writeb'? [-Werror=implicit-function-declaration] 221 | writesb(ctx->regs + reg, (const u8 *)val, val_count); | ^~~~~~~ | writeb drivers/base/regmap/regmap-mmio.c:224:17: error: implicit declaration of function 'writesw'; did you mean 'writew'? [-Werror=implicit-function-declaration] 224 | writesw(ctx->regs + reg, (const u16 *)val, val_count); | ^~~~~~~ | writew drivers/base/regmap/regmap-mmio.c:227:17: error: implicit declaration of function 'writesl'; did you mean 'writel'? [-Werror=implicit-function-declaration] 227 | writesl(ctx->regs + reg, (const u32 *)val, val_count); | ^~~~~~~ | writel >> drivers/base/regmap/regmap-mmio.c:231:17: error: implicit declaration of function 'writesq'; did you mean 'writeq'? [-Werror=implicit-function-declaration] 231 | writesq(ctx->regs + reg, (const u64 *)val, val_count); | ^~~~~~~ | writeq drivers/base/regmap/regmap-mmio.c: In function 'regmap_mmio_noinc_read': drivers/base/regmap/regmap-mmio.c:358:17: error: implicit declaration of function 'readsb'; did you mean 'readb'? [-Werror=implicit-function-declaration] 358 | readsb(ctx->regs + reg, (u8 *)val, val_count); | ^~~~~~ | readb drivers/base/regmap/regmap-mmio.c:361:17: error: implicit declaration of function 'readsw'; did you mean 'readw'? [-Werror=implicit-function-declaration] 361 | readsw(ctx->regs + reg, (u16 *)val, val_count); | ^~~~~~ | readw drivers/base/regmap/regmap-mmio.c:364:17: error: implicit declaration of function 'readsl'; did you mean 'readl'? [-Werror=implicit-function-declaration] 364 | readsl(ctx->regs + reg, (u32 *)val, val_count); | ^~~~~~ | readl >> drivers/base/regmap/regmap-mmio.c:368:17: error: implicit declaration of function 'readsq'; did you mean 'readq'? [-Werror=implicit-function-declaration] 368 | readsq(ctx->regs + reg, (u64 *)val, val_count); | ^~~~~~ | readq cc1: some warnings being treated as errors vim +231 drivers/base/regmap/regmap-mmio.c 168 169 static int regmap_mmio_noinc_write(void *context, unsigned int reg, 170 const void *val, size_t val_count) 171 { 172 struct regmap_mmio_context *ctx = context; 173 int ret = 0; 174 int i; 175 176 if (!IS_ERR(ctx->clk)) { 177 ret = clk_enable(ctx->clk); 178 if (ret < 0) 179 return ret; 180 } 181 182 /* 183 * There are no native, assembly-optimized write single register 184 * operations for big endian, so fall back to emulation if this 185 * is needed. (Single bytes are fine, they are not affected by 186 * endianness.) 187 */ 188 if (ctx->big_endian && (ctx->val_bytes > 1)) { 189 switch (ctx->val_bytes) { 190 case 2: 191 { 192 const u16 *valp = (const u16 *)val; 193 for (i = 0; i < val_count; i++) 194 writew(swab16(valp[i]), ctx->regs + reg); 195 goto out_clk; 196 } 197 case 4: 198 { 199 const u32 *valp = (const u32 *)val; 200 for (i = 0; i < val_count; i++) 201 writel(swab32(valp[i]), ctx->regs + reg); 202 goto out_clk; 203 } 204 #ifdef CONFIG_64BIT 205 case 8: 206 { 207 const u64 *valp = (const u64 *)val; 208 for (i = 0; i < val_count; i++) 209 writeq(swab64(valp[i]), ctx->regs + reg); 210 goto out_clk; 211 } 212 #endif 213 default: 214 ret = -EINVAL; 215 goto out_clk; 216 } 217 } 218 219 switch (ctx->val_bytes) { 220 case 1: 221 writesb(ctx->regs + reg, (const u8 *)val, val_count); 222 break; 223 case 2: 224 writesw(ctx->regs + reg, (const u16 *)val, val_count); 225 break; 226 case 4: 227 writesl(ctx->regs + reg, (const u32 *)val, val_count); 228 break; 229 #ifdef CONFIG_64BIT 230 case 8: > 231 writesq(ctx->regs + reg, (const u64 *)val, val_count); 232 break; 233 #endif 234 default: 235 ret = -EINVAL; 236 break; 237 } 238 239 out_clk: 240 if (!IS_ERR(ctx->clk)) 241 clk_disable(ctx->clk); 242 243 return ret; 244 } 245 246 static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx, 247 unsigned int reg) 248 { 249 return readb(ctx->regs + reg); 250 } 251 252 static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx, 253 unsigned int reg) 254 { 255 return readb_relaxed(ctx->regs + reg); 256 } 257 258 static unsigned int regmap_mmio_ioread8(struct regmap_mmio_context *ctx, 259 unsigned int reg) 260 { 261 return ioread8(ctx->regs + reg); 262 } 263 264 static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx, 265 unsigned int reg) 266 { 267 return readw(ctx->regs + reg); 268 } 269 270 static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx, 271 unsigned int reg) 272 { 273 return readw_relaxed(ctx->regs + reg); 274 } 275 276 static unsigned int regmap_mmio_ioread16le(struct regmap_mmio_context *ctx, 277 unsigned int reg) 278 { 279 return ioread16(ctx->regs + reg); 280 } 281 282 static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx, 283 unsigned int reg) 284 { 285 return swab16(readw(ctx->regs + reg)); 286 } 287 288 static unsigned int regmap_mmio_ioread16be(struct regmap_mmio_context *ctx, 289 unsigned int reg) 290 { 291 return ioread16be(ctx->regs + reg); 292 } 293 294 static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx, 295 unsigned int reg) 296 { 297 return readl(ctx->regs + reg); 298 } 299 300 static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx, 301 unsigned int reg) 302 { 303 return readl_relaxed(ctx->regs + reg); 304 } 305 306 static unsigned int regmap_mmio_ioread32le(struct regmap_mmio_context *ctx, 307 unsigned int reg) 308 { 309 return ioread32(ctx->regs + reg); 310 } 311 312 static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx, 313 unsigned int reg) 314 { 315 return swab32(readl(ctx->regs + reg)); 316 } 317 318 static unsigned int regmap_mmio_ioread32be(struct regmap_mmio_context *ctx, 319 unsigned int reg) 320 { 321 return ioread32be(ctx->regs + reg); 322 } 323 324 static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val) 325 { 326 struct regmap_mmio_context *ctx = context; 327 int ret; 328 329 if (!IS_ERR(ctx->clk)) { 330 ret = clk_enable(ctx->clk); 331 if (ret < 0) 332 return ret; 333 } 334 335 *val = ctx->reg_read(ctx, reg); 336 337 if (!IS_ERR(ctx->clk)) 338 clk_disable(ctx->clk); 339 340 return 0; 341 } 342 343 static int regmap_mmio_noinc_read(void *context, unsigned int reg, 344 void *val, size_t val_count) 345 { 346 struct regmap_mmio_context *ctx = context; 347 int ret = 0; 348 int i; 349 350 if (!IS_ERR(ctx->clk)) { 351 ret = clk_enable(ctx->clk); 352 if (ret < 0) 353 return ret; 354 } 355 356 switch (ctx->val_bytes) { 357 case 1: 358 readsb(ctx->regs + reg, (u8 *)val, val_count); 359 break; 360 case 2: 361 readsw(ctx->regs + reg, (u16 *)val, val_count); 362 break; 363 case 4: 364 readsl(ctx->regs + reg, (u32 *)val, val_count); 365 break; 366 #ifdef CONFIG_64BIT 367 case 8: > 368 readsq(ctx->regs + reg, (u64 *)val, val_count); 369 break; 370 #endif 371 default: 372 ret = -EINVAL; 373 goto out_clk; 374 } 375 376 /* 377 * There are no native, assembly-optimized write single register 378 * operations for big endian, so fall back to emulation if this 379 * is needed. (Single bytes are fine, they are not affected by 380 * endianness.) 381 */ 382 if (ctx->big_endian && (ctx->val_bytes > 1)) { 383 switch (ctx->val_bytes) { 384 case 2: 385 { 386 u16 *valp = (u16 *)val; 387 for (i = 0; i < val_count; i++) 388 valp[i] = swab16(valp[i]); 389 break; 390 } 391 case 4: 392 { 393 u32 *valp = (u32 *)val; 394 for (i = 0; i < val_count; i++) 395 valp[i] = swab32(valp[i]); 396 break; 397 } 398 #ifdef CONFIG_64BIT 399 case 8: 400 { 401 u64 *valp = (u64 *)val; 402 for (i = 0; i < val_count; i++) 403 valp[i] = swab64(valp[i]); 404 break; 405 } 406 #endif 407 default: 408 ret = -EINVAL; 409 break; 410 } 411 } 412 413 414 out_clk: 415 if (!IS_ERR(ctx->clk)) 416 clk_disable(ctx->clk); 417 418 return ret; 419 420 return 0; 421 } 422 -- 0-DAY CI Kernel Test Service https://01.org/lkp