From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3188C43334 for ; Sat, 11 Jun 2022 01:28:34 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id CBC1D8D00FC; Fri, 10 Jun 2022 21:28:33 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id C6B0D8D00F7; Fri, 10 Jun 2022 21:28:33 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id B33A98D00FC; Fri, 10 Jun 2022 21:28:33 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id A4F058D00F7 for ; Fri, 10 Jun 2022 21:28:33 -0400 (EDT) Received: from smtpin30.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 78F1061826 for ; Sat, 11 Jun 2022 01:28:33 +0000 (UTC) X-FDA: 79564220106.30.F88AE79 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by imf20.hostedemail.com (Postfix) with ESMTP id 949401C006E for ; Sat, 11 Jun 2022 01:28:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654910912; x=1686446912; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=6kbuoWn2/Np3kiQGVvTfuTgoBDbVE2L6Exk4Okh2Jl0=; b=Mm6IXm2kpZCK3d1svz47nlFVXuo683YRUrn23ebmG0IOTCJEwVXlnOxE 3JeIYiSJREFoMm92eH677Cja+Ryv+LI3lL1bGyIQsHDpP5kI05MQ40A0S oE1kchwRKsQHOZrw2AgQvJbM6yOL2vmtI88mYbabcb+RBOIX4LPDGl8zy HZgvlZeIxpuRp45i0hrhwjX48UHepp85SH91Tf97Z6839JgbDP0e/Hkjw 17pl4J/qmY2jv2POCcxy4BC7FZKXgchlKpCQZbXwNHDQUYCkqw66/9IsU iIf51+uPjnzjnnEqfd9WBInkkT7ytYuoGGpqVwBaMmhXmMzMpbC68vck0 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10374"; a="276579476" X-IronPort-AV: E=Sophos;i="5.91,292,1647327600"; d="scan'208";a="276579476" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 18:28:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,292,1647327600"; d="scan'208";a="650128436" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 10 Jun 2022 18:28:27 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id A4535F8; Sat, 11 Jun 2022 04:28:30 +0300 (EEST) Date: Sat, 11 Jun 2022 04:28:30 +0300 From: "Kirill A. Shutemov" To: Dave Hansen , Catalin Marinas , Will Deacon Cc: Dave Hansen , Andy Lutomirski , Peter Zijlstra , x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv3 7/8] x86: Expose untagging mask in /proc/$PID/arch_status Message-ID: <20220611012830.hs437yikbjgwlije@black.fi.intel.com> References: <20220610143527.22974-1-kirill.shutemov@linux.intel.com> <20220610143527.22974-8-kirill.shutemov@linux.intel.com> <144af1ab-1e7e-b75c-331c-d9c2e55b9062@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <144af1ab-1e7e-b75c-331c-d9c2e55b9062@intel.com> ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1654910913; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=vhgxF2lEh97gzlZOP+lXnLKPrYmePBk9rNrHORpGPaM=; b=IpzFV0RTU4Hv4kGZLPQAvjtQ0+Y9a0WGFwLTanorrIo6d/YaZOBnR9L525ufhfo6JvW0TY T5mSmY3SkL/GyJx7k3IuorZFyhyw1RAzYNSeynjDkIstLoZqbdw9tWzWjFEoAcvK4QMgeh pPav8AgrtbaqBsoqngeuK9Ox7kRLTms= ARC-Authentication-Results: i=1; imf20.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=Mm6IXm2k; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf20.hostedemail.com: domain of kirill.shutemov@linux.intel.com has no SPF policy when checking 192.55.52.120) smtp.mailfrom=kirill.shutemov@linux.intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1654910913; a=rsa-sha256; cv=none; b=INGu3Vu9ewqqtjCLW7mpxbVHawz5YrNXMhl/7cKM4zv3YDqaX3bcMV6OdCcAPuWGUCgSJy PMagCTPojNo/nKElhoTARQtTAWmh/bcZEoY8Qv8E8q9pkXDwbXxkX877eGt7EKkanXxFCx R+LyVnaNf5GgHYmPqdR6jo2APhxoMoM= X-Stat-Signature: mwj7u773srwzhqjjzw69ajsb9m8zewrd X-Rspamd-Queue-Id: 949401C006E Authentication-Results: imf20.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=Mm6IXm2k; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf20.hostedemail.com: domain of kirill.shutemov@linux.intel.com has no SPF policy when checking 192.55.52.120) smtp.mailfrom=kirill.shutemov@linux.intel.com X-Rspam-User: X-Rspamd-Server: rspam05 X-HE-Tag: 1654910912-244269 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Fri, Jun 10, 2022 at 08:24:38AM -0700, Dave Hansen wrote: > On 6/10/22 07:35, Kirill A. Shutemov wrote: > > +/* > > + * Report architecture specific information > > + */ > > +int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns, > > + struct pid *pid, struct task_struct *task) > > +{ > > + /* > > + * Report AVX512 state if the processor and build option supported. > > + */ > > + if (cpu_feature_enabled(X86_FEATURE_AVX512F)) > > + avx512_status(m, task); > > + > > + seq_printf(m, "untag_mask:\t%#lx\n", mm_untag_mask(task->mm)); > > + > > + return 0; > > +} > > Arch-specific gunk is great for, well, arch-specific stuff. AVX-512 and > its, um, "quirks", really won't show up anywhere else. But x86 isn't > even the first to be doing this address tagging business. > > Shouldn't we be talking to the ARM folks about a common way to do this? + Catalin, Will. I guess we can expose the mask via proc for ARM too, but I'm not sure if we can unify interface further without breaking existing TBI users: TBI is enabled per-thread while LAM is per-process. Any opinions? -- Kirill A. Shutemov