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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id b4sm17437326pfl.106.2022.02.08.17.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 17:10:31 -0800 (PST) Date: Tue, 8 Feb 2022 17:10:30 -0800 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Dave Martin , Weijiang Yang , "Kirill A . Shutemov" , joao.moreira@intel.com, John Allen , kcc@google.com, eranian@google.com, Yu-cheng Yu Subject: Re: [PATCH 03/35] x86/cpufeatures: Add CET CPU feature flags for Control-flow Enforcement Technology (CET) Message-ID: <202202081709.96226C0B@keescook> References: <20220130211838.8382-1-rick.p.edgecombe@intel.com> <20220130211838.8382-4-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220130211838.8382-4-rick.p.edgecombe@intel.com> X-Rspamd-Queue-Id: 95C7240002 Authentication-Results: imf04.hostedemail.com; dkim=pass header.d=chromium.org header.s=google header.b=B01e8AvR; spf=pass (imf04.hostedemail.com: domain of keescook@chromium.org designates 209.85.216.44 as permitted sender) smtp.mailfrom=keescook@chromium.org; dmarc=pass (policy=none) header.from=chromium.org X-Stat-Signature: sxtn84x3j8jf8z5rebekedweypojtp1s X-Rspam-User: X-Rspamd-Server: rspam10 X-HE-Tag: 1644369032-604485 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Sun, Jan 30, 2022 at 01:18:06PM -0800, Rick Edgecombe wrote: > From: Yu-cheng Yu > > Add CPU feature flags for Control-flow Enforcement Technology (CET). > > CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack > CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking It looks like this only adds the SHSTK bit, maybe drop mention of IBT here. I wonder if we could land this (and the IBT part) without waiting for everything else in the respective series? -Kees > > Signed-off-by: Yu-cheng Yu > Signed-off-by: Rick Edgecombe > Cc: Kees Cook > --- > > v1: > - Remove IBT, can be added in a follow on IBT series. > > Yu-cheng v25: > - Make X86_FEATURE_IBT depend on X86_FEATURE_SHSTK. > > Yu-cheng v24: > - Update for splitting CONFIG_X86_CET to CONFIG_X86_SHADOW_STACK and > CONFIG_X86_IBT. > - Move DISABLE_IBT definition to the IBT series. > > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/disabled-features.h | 8 +++++++- > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 6db4e2932b3d..c3eb94b13fef 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -355,6 +355,7 @@ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > #define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */ > #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ > +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */ > #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ > #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ > #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index 8f28fafa98b3..b7728f7afb2b 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -65,6 +65,12 @@ > # define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) > #endif > > +#ifdef CONFIG_X86_SHADOW_STACK > +#define DISABLE_SHSTK 0 > +#else > +#define DISABLE_SHSTK (1 << (X86_FEATURE_SHSTK & 31)) > +#endif > + > /* > * Make sure to add features to the correct mask > */ > @@ -85,7 +91,7 @@ > #define DISABLED_MASK14 0 > #define DISABLED_MASK15 0 > #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ > - DISABLE_ENQCMD) > + DISABLE_ENQCMD|DISABLE_SHSTK) > #define DISABLED_MASK17 0 > #define DISABLED_MASK18 0 > #define DISABLED_MASK19 0 > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c > index c881bcafba7d..bf1b55a1ba21 100644 > --- a/arch/x86/kernel/cpu/cpuid-deps.c > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > @@ -78,6 +78,7 @@ static const struct cpuid_dep cpuid_deps[] = { > { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, > { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, > { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, > + { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, > {} > }; > > -- > 2.17.1 > -- Kees Cook