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28 Jan 2022 15:48:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,325,1635231600"; d="scan'208";a="564352284" Received: from lkp-server01.sh.intel.com (HELO 276f1b88eecb) ([10.239.97.150]) by orsmga001.jf.intel.com with ESMTP; 28 Jan 2022 15:48:07 -0800 Received: from kbuild by 276f1b88eecb with local (Exim 4.92) (envelope-from ) id 1nDayM-000OSg-CB; Fri, 28 Jan 2022 23:48:06 +0000 Date: Sat, 29 Jan 2022 07:47:54 +0800 From: kernel test robot To: Kees Cook Cc: kbuild-all@lists.01.org, Linux Memory Management List , Arnd Bergmann , Nathan Chancellor , Nick Desaulniers , Masahiro Yamada , Andrew Morton Subject: [linux-next:master 2450/2855] drivers/dma/fsl-edma.c:302: undefined reference to `devm_ioremap_resource' Message-ID: <202201290705.x0MS0OCH-lkp@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: CC5B5A0006 X-Stat-Signature: ffi46mak1f1977xps8xnjnkg3qr8u8fn Authentication-Results: imf15.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=Mw9QOdAQ; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf15.hostedemail.com: domain of lkp@intel.com has no SPF policy when checking 192.55.52.151) smtp.mailfrom=lkp@intel.com X-Rspam-User: nil X-HE-Tag: 1643413690-198414 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: b605fdc54c2b28c30ef06d9db99282d8a32ae4be commit: 880f694bd1cef484e92065ea4e736850abce5352 [2450/2855] Kconfig.debug: make DEBUG_INFO selectable from a choice config: s390-randconfig-r021-20220127 (https://download.01.org/0day-ci/archive/20220129/202201290705.x0MS0OCH-lkp@intel.com/config) compiler: s390-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=880f694bd1cef484e92065ea4e736850abce5352 git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout 880f694bd1cef484e92065ea4e736850abce5352 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=s390 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): s390-linux-ld: drivers/dma/fsl-edma.o: in function `fsl_edma_probe': >> drivers/dma/fsl-edma.c:302: undefined reference to `devm_ioremap_resource' >> s390-linux-ld: drivers/dma/fsl-edma.c:327: undefined reference to `devm_ioremap_resource' s390-linux-ld: drivers/dma/qcom/hidma.o: in function `hidma_probe': >> drivers/dma/qcom/hidma.c:759: undefined reference to `devm_ioremap_resource' >> s390-linux-ld: drivers/dma/qcom/hidma.c:766: undefined reference to `devm_ioremap_resource' s390-linux-ld: drivers/char/xillybus/xillybus_of.o: in function `xilly_drv_probe': >> drivers/char/xillybus/xillybus_of.c:50: undefined reference to `devm_platform_ioremap_resource' s390-linux-ld: drivers/clocksource/timer-of.o: in function `timer_of_base_init': drivers/clocksource/timer-of.c:159: undefined reference to `of_iomap' s390-linux-ld: drivers/clocksource/timer-of.o: in function `timer_of_base_exit': drivers/clocksource/timer-of.c:151: undefined reference to `iounmap' s390-linux-ld: drivers/clocksource/timer-of.c:151: undefined reference to `iounmap' vim +302 drivers/dma/fsl-edma.c af802728e4ab07 Robin Gong 2019-06-25 265 d6be34fbd39b7d Jingchang Lu 2014-02-18 266 static int fsl_edma_probe(struct platform_device *pdev) d6be34fbd39b7d Jingchang Lu 2014-02-18 267 { af802728e4ab07 Robin Gong 2019-06-25 268 const struct of_device_id *of_id = af802728e4ab07 Robin Gong 2019-06-25 269 of_match_device(fsl_edma_dt_ids, &pdev->dev); d6be34fbd39b7d Jingchang Lu 2014-02-18 270 struct device_node *np = pdev->dev.of_node; d6be34fbd39b7d Jingchang Lu 2014-02-18 271 struct fsl_edma_engine *fsl_edma; af802728e4ab07 Robin Gong 2019-06-25 272 const struct fsl_edma_drvdata *drvdata = NULL; d6be34fbd39b7d Jingchang Lu 2014-02-18 273 struct fsl_edma_chan *fsl_chan; 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 274 struct edma_regs *regs; d6be34fbd39b7d Jingchang Lu 2014-02-18 275 struct resource *res; d6be34fbd39b7d Jingchang Lu 2014-02-18 276 int len, chans; d6be34fbd39b7d Jingchang Lu 2014-02-18 277 int ret, i; d6be34fbd39b7d Jingchang Lu 2014-02-18 278 af802728e4ab07 Robin Gong 2019-06-25 279 if (of_id) af802728e4ab07 Robin Gong 2019-06-25 280 drvdata = of_id->data; af802728e4ab07 Robin Gong 2019-06-25 281 if (!drvdata) { af802728e4ab07 Robin Gong 2019-06-25 282 dev_err(&pdev->dev, "unable to find driver data\n"); af802728e4ab07 Robin Gong 2019-06-25 283 return -EINVAL; af802728e4ab07 Robin Gong 2019-06-25 284 } af802728e4ab07 Robin Gong 2019-06-25 285 d6be34fbd39b7d Jingchang Lu 2014-02-18 286 ret = of_property_read_u32(np, "dma-channels", &chans); d6be34fbd39b7d Jingchang Lu 2014-02-18 287 if (ret) { d6be34fbd39b7d Jingchang Lu 2014-02-18 288 dev_err(&pdev->dev, "Can't get dma-channels.\n"); d6be34fbd39b7d Jingchang Lu 2014-02-18 289 return ret; d6be34fbd39b7d Jingchang Lu 2014-02-18 290 } d6be34fbd39b7d Jingchang Lu 2014-02-18 291 d6be34fbd39b7d Jingchang Lu 2014-02-18 292 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans; d6be34fbd39b7d Jingchang Lu 2014-02-18 293 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); d6be34fbd39b7d Jingchang Lu 2014-02-18 294 if (!fsl_edma) d6be34fbd39b7d Jingchang Lu 2014-02-18 295 return -ENOMEM; d6be34fbd39b7d Jingchang Lu 2014-02-18 296 af802728e4ab07 Robin Gong 2019-06-25 297 fsl_edma->drvdata = drvdata; d6be34fbd39b7d Jingchang Lu 2014-02-18 298 fsl_edma->n_chans = chans; d6be34fbd39b7d Jingchang Lu 2014-02-18 299 mutex_init(&fsl_edma->fsl_edma_mutex); d6be34fbd39b7d Jingchang Lu 2014-02-18 300 d6be34fbd39b7d Jingchang Lu 2014-02-18 301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); d6be34fbd39b7d Jingchang Lu 2014-02-18 @302 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); d6be34fbd39b7d Jingchang Lu 2014-02-18 303 if (IS_ERR(fsl_edma->membase)) d6be34fbd39b7d Jingchang Lu 2014-02-18 304 return PTR_ERR(fsl_edma->membase); d6be34fbd39b7d Jingchang Lu 2014-02-18 305 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 306 fsl_edma_setup_regs(fsl_edma); 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 307 regs = &fsl_edma->regs; 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 308 232a7f18cf8ecb Robin Gong 2019-07-24 309 if (drvdata->has_dmaclk) { 232a7f18cf8ecb Robin Gong 2019-07-24 310 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); 232a7f18cf8ecb Robin Gong 2019-07-24 311 if (IS_ERR(fsl_edma->dmaclk)) { 232a7f18cf8ecb Robin Gong 2019-07-24 312 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 232a7f18cf8ecb Robin Gong 2019-07-24 313 return PTR_ERR(fsl_edma->dmaclk); 232a7f18cf8ecb Robin Gong 2019-07-24 314 } 232a7f18cf8ecb Robin Gong 2019-07-24 315 232a7f18cf8ecb Robin Gong 2019-07-24 316 ret = clk_prepare_enable(fsl_edma->dmaclk); 232a7f18cf8ecb Robin Gong 2019-07-24 317 if (ret) { 232a7f18cf8ecb Robin Gong 2019-07-24 318 dev_err(&pdev->dev, "DMA clk block failed.\n"); 232a7f18cf8ecb Robin Gong 2019-07-24 319 return ret; 232a7f18cf8ecb Robin Gong 2019-07-24 320 } 232a7f18cf8ecb Robin Gong 2019-07-24 321 } 232a7f18cf8ecb Robin Gong 2019-07-24 322 af802728e4ab07 Robin Gong 2019-06-25 323 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { d6be34fbd39b7d Jingchang Lu 2014-02-18 324 char clkname[32]; d6be34fbd39b7d Jingchang Lu 2014-02-18 325 d6be34fbd39b7d Jingchang Lu 2014-02-18 326 res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i); d6be34fbd39b7d Jingchang Lu 2014-02-18 @327 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res); 2610acf46b9ed5 Andreas Platschek 2017-12-14 328 if (IS_ERR(fsl_edma->muxbase[i])) { 2610acf46b9ed5 Andreas Platschek 2017-12-14 329 /* on error: disable all previously enabled clks */ 2610acf46b9ed5 Andreas Platschek 2017-12-14 330 fsl_disable_clocks(fsl_edma, i); d6be34fbd39b7d Jingchang Lu 2014-02-18 331 return PTR_ERR(fsl_edma->muxbase[i]); 2610acf46b9ed5 Andreas Platschek 2017-12-14 332 } d6be34fbd39b7d Jingchang Lu 2014-02-18 333 d6be34fbd39b7d Jingchang Lu 2014-02-18 334 sprintf(clkname, "dmamux%d", i); d6be34fbd39b7d Jingchang Lu 2014-02-18 335 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); d6be34fbd39b7d Jingchang Lu 2014-02-18 336 if (IS_ERR(fsl_edma->muxclk[i])) { d6be34fbd39b7d Jingchang Lu 2014-02-18 337 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 2610acf46b9ed5 Andreas Platschek 2017-12-14 338 /* on error: disable all previously enabled clks */ 2610acf46b9ed5 Andreas Platschek 2017-12-14 339 fsl_disable_clocks(fsl_edma, i); d6be34fbd39b7d Jingchang Lu 2014-02-18 340 return PTR_ERR(fsl_edma->muxclk[i]); d6be34fbd39b7d Jingchang Lu 2014-02-18 341 } d6be34fbd39b7d Jingchang Lu 2014-02-18 342 d6be34fbd39b7d Jingchang Lu 2014-02-18 343 ret = clk_prepare_enable(fsl_edma->muxclk[i]); 2610acf46b9ed5 Andreas Platschek 2017-12-14 344 if (ret) 2610acf46b9ed5 Andreas Platschek 2017-12-14 345 /* on error: disable all previously enabled clks */ 2610acf46b9ed5 Andreas Platschek 2017-12-14 346 fsl_disable_clocks(fsl_edma, i); d6be34fbd39b7d Jingchang Lu 2014-02-18 347 d6be34fbd39b7d Jingchang Lu 2014-02-18 348 } d6be34fbd39b7d Jingchang Lu 2014-02-18 349 d6be34fbd39b7d Jingchang Lu 2014-02-18 350 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); d6be34fbd39b7d Jingchang Lu 2014-02-18 351 d6be34fbd39b7d Jingchang Lu 2014-02-18 352 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); d6be34fbd39b7d Jingchang Lu 2014-02-18 353 for (i = 0; i < fsl_edma->n_chans; i++) { d6be34fbd39b7d Jingchang Lu 2014-02-18 354 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; d6be34fbd39b7d Jingchang Lu 2014-02-18 355 d6be34fbd39b7d Jingchang Lu 2014-02-18 356 fsl_chan->edma = fsl_edma; 82d149b86d31e1 Yuan Yao 2015-10-30 357 fsl_chan->pm_state = RUNNING; 82d149b86d31e1 Yuan Yao 2015-10-30 358 fsl_chan->slave_id = 0; 82d149b86d31e1 Yuan Yao 2015-10-30 359 fsl_chan->idle = true; 0fa89f972da607 Laurentiu Tudor 2019-01-18 360 fsl_chan->dma_dir = DMA_NONE; d6be34fbd39b7d Jingchang Lu 2014-02-18 361 fsl_chan->vchan.desc_free = fsl_edma_free_desc; d6be34fbd39b7d Jingchang Lu 2014-02-18 362 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); d6be34fbd39b7d Jingchang Lu 2014-02-18 363 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 364 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); d6be34fbd39b7d Jingchang Lu 2014-02-18 365 fsl_edma_chan_mux(fsl_chan, 0, false); d6be34fbd39b7d Jingchang Lu 2014-02-18 366 } d6be34fbd39b7d Jingchang Lu 2014-02-18 367 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 368 edma_writel(fsl_edma, ~0, regs->intl); af802728e4ab07 Robin Gong 2019-06-25 369 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 0fe25d61102d44 Stefan Agner 2015-06-07 370 if (ret) 0fe25d61102d44 Stefan Agner 2015-06-07 371 return ret; 0fe25d61102d44 Stefan Agner 2015-06-07 372 d6be34fbd39b7d Jingchang Lu 2014-02-18 373 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); d6be34fbd39b7d Jingchang Lu 2014-02-18 374 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); d6be34fbd39b7d Jingchang Lu 2014-02-18 375 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); e0674853943287 Joy Zou 2021-10-26 376 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); d6be34fbd39b7d Jingchang Lu 2014-02-18 377 d6be34fbd39b7d Jingchang Lu 2014-02-18 378 fsl_edma->dma_dev.dev = &pdev->dev; d6be34fbd39b7d Jingchang Lu 2014-02-18 379 fsl_edma->dma_dev.device_alloc_chan_resources d6be34fbd39b7d Jingchang Lu 2014-02-18 380 = fsl_edma_alloc_chan_resources; d6be34fbd39b7d Jingchang Lu 2014-02-18 381 fsl_edma->dma_dev.device_free_chan_resources d6be34fbd39b7d Jingchang Lu 2014-02-18 382 = fsl_edma_free_chan_resources; d6be34fbd39b7d Jingchang Lu 2014-02-18 383 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; d6be34fbd39b7d Jingchang Lu 2014-02-18 384 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; d6be34fbd39b7d Jingchang Lu 2014-02-18 385 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; e0674853943287 Joy Zou 2021-10-26 386 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; d80f381f321ab7 Maxime Ripard 2014-11-17 387 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; d80f381f321ab7 Maxime Ripard 2014-11-17 388 fsl_edma->dma_dev.device_pause = fsl_edma_pause; d80f381f321ab7 Maxime Ripard 2014-11-17 389 fsl_edma->dma_dev.device_resume = fsl_edma_resume; d80f381f321ab7 Maxime Ripard 2014-11-17 390 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; ba1cab79cfc629 Andrey Smirnov 2019-07-31 391 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; d6be34fbd39b7d Jingchang Lu 2014-02-18 392 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; f45c431148e1ba Maxime Ripard 2014-11-17 393 f45c431148e1ba Maxime Ripard 2014-11-17 394 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; f45c431148e1ba Maxime Ripard 2014-11-17 395 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; f45c431148e1ba Maxime Ripard 2014-11-17 396 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); d6be34fbd39b7d Jingchang Lu 2014-02-18 397 e0674853943287 Joy Zou 2021-10-26 398 fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES; e0674853943287 Joy Zou 2021-10-26 399 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ e0674853943287 Joy Zou 2021-10-26 400 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); e0674853943287 Joy Zou 2021-10-26 401 d6be34fbd39b7d Jingchang Lu 2014-02-18 402 platform_set_drvdata(pdev, fsl_edma); d6be34fbd39b7d Jingchang Lu 2014-02-18 403 d6be34fbd39b7d Jingchang Lu 2014-02-18 404 ret = dma_async_device_register(&fsl_edma->dma_dev); d6be34fbd39b7d Jingchang Lu 2014-02-18 405 if (ret) { a86144da9d1a43 Peter Griffin 2016-06-07 406 dev_err(&pdev->dev, a86144da9d1a43 Peter Griffin 2016-06-07 407 "Can't register Freescale eDMA engine. (%d)\n", ret); af802728e4ab07 Robin Gong 2019-06-25 408 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); d6be34fbd39b7d Jingchang Lu 2014-02-18 409 return ret; d6be34fbd39b7d Jingchang Lu 2014-02-18 410 } d6be34fbd39b7d Jingchang Lu 2014-02-18 411 d6be34fbd39b7d Jingchang Lu 2014-02-18 412 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma); d6be34fbd39b7d Jingchang Lu 2014-02-18 413 if (ret) { a86144da9d1a43 Peter Griffin 2016-06-07 414 dev_err(&pdev->dev, a86144da9d1a43 Peter Griffin 2016-06-07 415 "Can't register Freescale eDMA of_dma. (%d)\n", ret); d6be34fbd39b7d Jingchang Lu 2014-02-18 416 dma_async_device_unregister(&fsl_edma->dma_dev); af802728e4ab07 Robin Gong 2019-06-25 417 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); d6be34fbd39b7d Jingchang Lu 2014-02-18 418 return ret; d6be34fbd39b7d Jingchang Lu 2014-02-18 419 } d6be34fbd39b7d Jingchang Lu 2014-02-18 420 d6be34fbd39b7d Jingchang Lu 2014-02-18 421 /* enable round robin arbitration */ 377eaf3b3c4ad7 Angelo Dureghello 2018-08-19 422 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); d6be34fbd39b7d Jingchang Lu 2014-02-18 423 d6be34fbd39b7d Jingchang Lu 2014-02-18 424 return 0; d6be34fbd39b7d Jingchang Lu 2014-02-18 425 } d6be34fbd39b7d Jingchang Lu 2014-02-18 426 :::::: The code at line 302 was first introduced by commit :::::: d6be34fbd39b7d577d25cb4edec538e8990ba07c dma: Add Freescale eDMA engine driver support :::::: TO: Jingchang Lu :::::: CC: Vinod Koul --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org