From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1313CC433EF for ; Thu, 11 Nov 2021 08:59:16 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id AC05061267 for ; Thu, 11 Nov 2021 08:59:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AC05061267 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvack.org Received: by kanga.kvack.org (Postfix) id 3F8C46B0072; Thu, 11 Nov 2021 03:59:15 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 3A7AB6B007E; Thu, 11 Nov 2021 03:59:15 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 26EDD6B009F; Thu, 11 Nov 2021 03:59:15 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0058.hostedemail.com [216.40.44.58]) by kanga.kvack.org (Postfix) with ESMTP id 141176B0072 for ; Thu, 11 Nov 2021 03:59:15 -0500 (EST) Received: from smtpin20.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id BF6F482267 for ; Thu, 11 Nov 2021 08:59:14 +0000 (UTC) X-FDA: 78796050228.20.2539E60 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf08.hostedemail.com (Postfix) with ESMTP id 869863000243 for ; Thu, 11 Nov 2021 08:58:59 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 8787B61208; Thu, 11 Nov 2021 08:59:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1636621153; bh=V/voYJdoZA1WY8AEKTOUrS/Vy3/qzbpOQsGhfSmMFw8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RDS3QmtEOrEJN86RtpjiUC0g3VTKJEznJ7GYHgWifBXd/43aiFvHghj+ZWzGVzR2k TIuFyfA+BOFkSbQcz6vfsnYkBtyDP/wEbl5ODtcAib3g/WqHphiMYGNqBFcy98j3jh upKkRms3N7wwml5TencLSL0R/0AiQeDPz9/hPNQPp3L2eRmnl2CinLtG2lUzV39WuY TkkcKZYza+f7g+sDZyEcbgqIGc+tUMLZ2KZaq5j4FKlT59z+paZLRdOgI1xl6tqN4h +95phXRgsnqqOegHYylKgiublk3jCaXmTmm9b+bo2G4V75SiDf4uKyqPtd1vWXkhVc E1eGCsxbbz4yA== Date: Thu, 11 Nov 2021 08:59:08 +0000 From: Will Deacon To: Yu Zhao Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, page-reclaim@google.com, holger@applied-asynchrony.com, iam@valdikss.org.ru, Konstantin Kharlamov , catalin.marinas@arm.com Subject: Re: [PATCH v5 01/10] mm: x86, arm64: add arch_has_hw_pte_young() Message-ID: <20211111085907.GA5407@willie-the-truck> References: <20211111041510.402534-1-yuzhao@google.com> <20211111041510.402534-2-yuzhao@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211111041510.402534-2-yuzhao@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) Authentication-Results: imf08.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=RDS3QmtE; spf=pass (imf08.hostedemail.com: domain of will@kernel.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=will@kernel.org; dmarc=pass (policy=none) header.from=kernel.org X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 869863000243 X-Stat-Signature: bdtokpium7rbjd8p4bwhy3onx9qegy73 X-HE-Tag: 1636621139-990974 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Nov 10, 2021 at 09:15:01PM -0700, Yu Zhao wrote: > Some architectures automatically set the accessed bit in PTEs, e.g., > x86 and arm64 v8.2. On architectures that do not have this capability, > clearing the accessed bit in a PTE triggers a page fault following the > TLB miss of this PTE. > > Being aware of this capability can help make better decisions, i.e., > whether to limit the size of each batch of PTEs and the burst of > batches when clearing the accessed bit. > > Signed-off-by: Yu Zhao > Tested-by: Konstantin Kharlamov > --- > arch/arm64/include/asm/cpufeature.h | 5 +++++ > arch/arm64/include/asm/pgtable.h | 13 ++++++++----- > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > arch/x86/include/asm/pgtable.h | 6 +++--- > include/linux/pgtable.h | 13 +++++++++++++ > mm/memory.c | 14 +------------- > 7 files changed, 41 insertions(+), 21 deletions(-) *Please* cc the maintainers on arch patches. I asked you that last time, too: https://lore.kernel.org/r/20210819091923.GA15467@willie-the-truck > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6ec7036ef7e1..940615d33845 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2157,6 +2157,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_hw_dbm, > .cpu_enable = cpu_enable_hw_dbm, > }, > + { > + .desc = "Hardware update of the Access flag", > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .capability = ARM64_HW_AF, > + .sys_reg = SYS_ID_AA64MMFR1_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR1_HADBS_SHIFT, > + .min_field_value = 1, > + .matches = has_cpuid_feature, > + }, As before, please don't make this a system feature as it will prohibit onlining of late CPUs with mismatched access flag support and I really don't see that being necessary. You should just be able to use arch_faults_on_old_pte() as-is. Will