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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 12/42] x86/compressed: Add helper for validating pages in the decompression stage Date: Fri, 8 Oct 2021 13:04:23 -0500 Message-ID: <20211008180453.462291-13-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c4df35a0-3ff2-4679-c5e3-08d98a863ad2 X-MS-TrafficTypeDiagnostic: DM6PR12MB4452: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qEFfQBDmCn0qDJoJh7L3c62UnqPGuNVuRPt2GlsjrnkMnCTFWV3OrUT6WlSlIaHawSFIay+LN/nNLy2CB2UDOQekOXLrKQrOW9LZFy2V9Hiv7N8pAdFpteQacKQpc26hReoxDBu/erCe8Q7F61oX4DuwHURkARW0d+nGuboD1uxb7mtXnKkQxkkCpB29cpUKfjc8UM6TGxj99iOMmc8iW50zE2R46Mh1ZKTrlK5z9B6cQq0lIXhMeZ1ttTKBRshdDkocCsYvJ1aN+NRD7meLVPmfrjGcDUsUbnYzaVDRuCiZxZzuUXSLSqNDITMV5dU9OjPt3f+ysrW1KO3AXGhrJLccVgKbHmn/r1atG3DoHuvJeBP2T/HUrXM+NNiMlaFBYzLt0+o1IGnGVWW5mhPveNl+8fhtoB3HTaZU0ZDF8ieTkLOMYj1xKBAaGwpdyKOUCZNGum3Yem98KiJr2KJTda2ioeeAIuK8td0p6I9nETAKaMV+zeob1fL5wofhaAOtiTbp0MzSfJy/Q0Zse+qBcihvRi6ZXXuxBy05hBPJE0Nr1hkCAA5qnQS/W2yOUKkK9N1nvabYv1kN1jA4kf+Nl0deX6vS0afmmLICr7dx9pwLCCu4IJhnFjE938VYtY4c5AKBkzHtmPaRC7XdfhtB16OGjztMbO7ArcA351Dy/2g/SGKBOrXycFuq1AEs47G0qBzY73alYJizcT0KWjeUFZMMFwit9LvaFtCOI5HmZgqC3GM7pCwXprX9mPd1Wa7O X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7696005)(26005)(7416002)(7406005)(186003)(5660300002)(83380400001)(8676002)(16526019)(8936002)(508600001)(82310400003)(6666004)(86362001)(47076005)(70586007)(1076003)(70206006)(426003)(2616005)(36860700001)(81166007)(316002)(4326008)(2906002)(44832011)(336012)(110136005)(36756003)(54906003)(356005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:36.5199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4df35a0-3ff2-4679-c5e3-08d98a863ad2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4452 X-Rspamd-Queue-Id: 0FA37B001390 X-Stat-Signature: xknnrw3ks4118nq7ebs1s7qeb8ngorrf Authentication-Results: imf24.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="bReNwj/J"; spf=pass (imf24.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.81 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716339-501559 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Many of the integrity guarantees of SEV-SNP are enforced through the Reverse Map Table (RMP). Each RMP entry contains the GPA at which a particular page of DRAM should be mapped. The VMs can request the hypervisor to add pages in the RMP table via the Page State Change VMGEXI= T defined in the GHCB specification. Inside each RMP entry is a Validated flag; this flag is automatically cleared to 0 by the CPU hardware when a new RMP entry is created for a guest. Each VM page can be either validated or invalidated, as indicated by the Validated flag in the RMP entry. Memory access to a private page that is not validated generates a #VC. A VM must use PVALIDATE instruction to validate the private page before using it. To maintain the security guarantee of SEV-SNP guests, when transitioning pages from private to shared, the guest must invalidate the pages before asking the hypervisor to change the page state to shared in the RMP table= . After the pages are mapped private in the page table, the guest must issu= e a page state change VMGEXIT to make the pages private in the RMP table an= d validate it. On boot, BIOS should have validated the entire system memory. During the kernel decompression stage, the VC handler uses the set_memory_decrypted() to make the GHCB page shared (i.e clear encryption attribute). And while exiting from the decompression, it calls the set_page_encrypted() to make the page private. Add sev_snp_set_page_{private,shared}() helper that is used by the set_memory_{decrypt,encrypt}() to change the page state in the RMP table. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/ident_map_64.c | 18 ++++++++++- arch/x86/boot/compressed/misc.h | 6 ++++ arch/x86/boot/compressed/sev.c | 41 +++++++++++++++++++++++++ arch/x86/include/asm/sev-common.h | 26 ++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/comp= ressed/ident_map_64.c index f7213d0943b8..3cf7a7575f5c 100644 --- a/arch/x86/boot/compressed/ident_map_64.c +++ b/arch/x86/boot/compressed/ident_map_64.c @@ -275,15 +275,31 @@ static int set_clr_page_flags(struct x86_mapping_in= fo *info, * Changing encryption attributes of a page requires to flush it from * the caches. */ - if ((set | clr) & _PAGE_ENC) + if ((set | clr) & _PAGE_ENC) { clflush_page(address); =20 + /* + * If the encryption attribute is being cleared, then change + * the page state to shared in the RMP table. + */ + if (clr) + snp_set_page_shared(pte_pfn(*ptep) << PAGE_SHIFT); + } + /* Update PTE */ pte =3D *ptep; pte =3D pte_set_flags(pte, set); pte =3D pte_clear_flags(pte, clr); set_pte(ptep, pte); =20 + /* + * If the encryption attribute is being set, then change the page state= to + * private in the RMP entry. The page state must be done after the PTE + * is updated. + */ + if (set & _PAGE_ENC) + snp_set_page_private(pte_pfn(*ptep) << PAGE_SHIFT); + /* Flush TLB after changing encryption attribute */ write_cr3(top_level_pgt); =20 diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/m= isc.h index 31139256859f..822e0c254b9a 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -121,12 +121,18 @@ void set_sev_encryption_mask(void); #ifdef CONFIG_AMD_MEM_ENCRYPT void sev_es_shutdown_ghcb(void); extern bool sev_es_check_ghcb_fault(unsigned long address); +void snp_set_page_private(unsigned long paddr); +void snp_set_page_shared(unsigned long paddr); + #else static inline void sev_es_shutdown_ghcb(void) { } static inline bool sev_es_check_ghcb_fault(unsigned long address) { return false; } +static inline void snp_set_page_private(unsigned long paddr) { } +static inline void snp_set_page_shared(unsigned long paddr) { } + #endif =20 /* acpi.c */ diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/se= v.c index cf24cc2af40a..c644f260098e 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -154,6 +154,47 @@ static bool is_vmpl0(void) return true; } =20 +static void __page_state_change(unsigned long paddr, enum psc_op op) +{ + u64 val; + + if (!sev_snp_enabled()) + return; + + /* + * If private -> shared then invalidate the page before requesting the + * state change in the RMP table. + */ + if (op =3D=3D SNP_PAGE_STATE_SHARED && pvalidate(paddr, RMP_PG_SIZE_4K,= 0)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); + + /* Issue VMGEXIT to change the page state in RMP table. */ + sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); + VMGEXIT(); + + /* Read the response of the VMGEXIT. */ + val =3D sev_es_rd_ghcb_msr(); + if ((GHCB_RESP_CODE(val) !=3D GHCB_MSR_PSC_RESP) || GHCB_MSR_PSC_RESP_V= AL(val)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); + + /* + * Now that page is added in the RMP table, validate it so that it is + * consistent with the RMP entry. + */ + if (op =3D=3D SNP_PAGE_STATE_PRIVATE && pvalidate(paddr, RMP_PG_SIZE_4K= , 1)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); +} + +void snp_set_page_private(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_PRIVATE); +} + +void snp_set_page_shared(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_SHARED); +} + static bool do_early_sev_setup(void) { if (!sev_es_negotiate_protocol()) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev= -common.h index d426c30ae7b4..1c76b6b775cc 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -57,6 +57,32 @@ #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 =20 +/* + * SNP Page State Change Operation + * + * GHCBData[55:52] - Page operation: + * 0x0001 =E2=80=93 Page assignment, Private + * 0x0002 =E2=80=93 Page assignment, Shared + */ +enum psc_op { + SNP_PAGE_STATE_PRIVATE =3D 1, + SNP_PAGE_STATE_SHARED, +}; + +#define GHCB_MSR_PSC_REQ 0x014 +#define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ + /* GHCBData[55:52] */ \ + (((u64)((op) & 0xf) << 52) | \ + /* GHCBData[51:12] */ \ + ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ + /* GHCBData[11:0] */ \ + GHCB_MSR_PSC_REQ) + +#define GHCB_MSR_PSC_RESP 0x015 +#define GHCB_MSR_PSC_RESP_VAL(val) \ + /* GHCBData[63:32] */ \ + (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) + /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081 --=20 2.25.1