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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1628642600; bh=ALJrrGc6ovgV0DuDRmC1sw13c6c8XRN1Ta2YoCgCtk8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CN7kjHjEJKlf7pYQhCwbva8FhCN0JrpHf0lPuJGgsbNcMyWCLb6FuxHHHMH6Gsuyi 77eEhwoGxcXUZexu83WSrfDFXWGxaXY2JzLGAKFgvWYXUcM9Ynmx71I0sGiW7XVxDp H++DJ7Ee8iwEj9HYBKi7JT4VaiW0qM9ZqP4IFI8p8onJvTtSgdKuGBrQHL2ZikMypN sb0MGUPqJmr089evcC1CnuzDZHe3pcPOQOVF+s+PmHvzQOUyQUumLJ4iJrQ1g08rQo aRZ2kd1bLswsExSdBtwxu+rEvXMd0TXUmMjePX9duerkkEgXQEe/0xv/htz9hX/Utn cba0kb11dVa6w== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Anshuman Khandual , Mike Rapoport , Vineet Gupta Subject: [PATCH 10/18] ARC: mm: move MMU specific bits out of ASID allocator Date: Tue, 10 Aug 2021 17:42:50 -0700 Message-Id: <20210811004258.138075-11-vgupta@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210811004258.138075-1-vgupta@kernel.org> References: <20210811004258.138075-1-vgupta@kernel.org> MIME-Version: 1.0 Authentication-Results: imf14.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=CN7kjHjE; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf14.hostedemail.com: domain of vgupta@kernel.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=vgupta@kernel.org X-Stat-Signature: stmpaj9ycttne4guzhq77qsyb8dfmkww X-Rspamd-Queue-Id: 90146600AAAC X-Rspamd-Server: rspam01 X-HE-Tag: 1628642601-12271 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: And while at it, rewrite commentary on ASID allocator Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu.h | 13 +++++++++++++ arch/arc/include/asm/mmu_context.h | 28 +++++++++++++--------------- arch/arc/mm/tlb.c | 11 ++++------- 3 files changed, 30 insertions(+), 22 deletions(-) diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h index 762cfe66e16b..2cabdfaf2afb 100644 --- a/arch/arc/include/asm/mmu.h +++ b/arch/arc/include/asm/mmu.h @@ -64,6 +64,19 @@ typedef struct { unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ } mm_context_t; =20 +static void inline mmu_setup_asid(struct mm_struct *mm, unsigned int asi= d) +{ + write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); +} + +static void inline mmu_setup_pgd(struct mm_struct *mm, pgd_t *pgd) +{ + /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ +#ifdef CONFIG_ISA_ARCV2 + write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); +#endif +} + static inline int is_pae40_enabled(void) { return IS_ENABLED(CONFIG_ARC_HAS_PAE40); diff --git a/arch/arc/include/asm/mmu_context.h b/arch/arc/include/asm/mm= u_context.h index 49318a126879..dda471f5f05b 100644 --- a/arch/arc/include/asm/mmu_context.h +++ b/arch/arc/include/asm/mmu_context.h @@ -15,22 +15,23 @@ #ifndef _ASM_ARC_MMU_CONTEXT_H #define _ASM_ARC_MMU_CONTEXT_H =20 -#include -#include #include =20 +#include #include =20 -/* ARC700 ASID Management +/* ARC ASID Management + * + * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on + * context-switch. * - * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing ent= ries - * with same vaddr (different tasks) to co-exit. This provides for - * "Fast Context Switch" i.e. no TLB flush on ctxt-switch + * ASID is managed per cpu, so task threads across CPUs can have differe= nt + * ASID. Global ASID management is needed if hardware supports TLB shoot= down + * and/or shared TLB across cores, which ARC doesn't. * - * Linux assigns each task a unique ASID. A simple round-robin allocatio= n - * of H/w ASID is done using software tracker @asid_cpu. - * When it reaches max 255, the allocation cycle starts afresh by flushi= ng - * the entire TLB and wrapping ASID back to zero. + * Each task is assigned unique ASID, with a simple round-robin allocato= r + * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is star= ted + * over from 0, and TLB is flushed * * A new allocation cycle, post rollover, could potentially reassign an = ASID * to a different task. Thus the rule is to refresh the ASID in a new cy= cle. @@ -93,7 +94,7 @@ static inline void get_new_mmu_context(struct mm_struct= *mm) asid_mm(mm, cpu) =3D asid_cpu(cpu); =20 set_hw: - write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE); + mmu_setup_asid(mm, hw_pid(mm, cpu)); =20 local_irq_restore(flags); } @@ -146,10 +147,7 @@ static inline void switch_mm(struct mm_struct *prev,= struct mm_struct *next, */ cpumask_set_cpu(cpu, mm_cpumask(next)); =20 -#ifdef CONFIG_ISA_ARCV2 - /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ - write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd); -#endif + mmu_setup_pgd(next, next->pgd); =20 get_new_mmu_context(next); } diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 15cbc285b0de..b68d5798327b 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -716,14 +716,11 @@ void arc_mmu_init(void) if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae) panic("Hardware doesn't support PAE40\n"); =20 - /* Enable the MMU */ - write_aux_reg(ARC_REG_PID, MMU_ENABLE); + /* Enable the MMU with ASID 0 */ + mmu_setup_asid(NULL, 0); =20 - /* In arc700/smp needed for re-entrant interrupt handling */ -#ifdef CONFIG_ISA_ARCV2 - /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */ - write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir); -#endif + /* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */ + mmu_setup_pgd(NULL, swapper_pg_dir); =20 if (pae40_exist_but_not_enab()) write_aux_reg(ARC_REG_TLBPD1HI, 0); --=20 2.25.1