From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D631C48BE6 for ; Wed, 16 Jun 2021 04:58:09 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id CFA4C610A0 for ; Wed, 16 Jun 2021 04:58:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CFA4C610A0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 73D1F6B0070; Wed, 16 Jun 2021 00:58:08 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 704AB6B0071; Wed, 16 Jun 2021 00:58:08 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 57DEA6B0072; Wed, 16 Jun 2021 00:58:08 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0211.hostedemail.com [216.40.44.211]) by kanga.kvack.org (Postfix) with ESMTP id 2624E6B0070 for ; Wed, 16 Jun 2021 00:58:08 -0400 (EDT) Received: from smtpin30.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id C627BA8CB for ; Wed, 16 Jun 2021 04:58:07 +0000 (UTC) X-FDA: 78258380214.30.42EECCE Received: from smtprelay.hostedemail.com (smtprelay0093.hostedemail.com [216.40.44.93]) by imf20.hostedemail.com (Postfix) with ESMTP id 9C9D6F2 for ; Wed, 16 Jun 2021 04:57:54 +0000 (UTC) Received: from forelay.hostedemail.com (clb03-v110.bra.tucows.net [216.40.38.60]) by smtprelay01.hostedemail.com (Postfix) with ESMTP id 0B52B100E7B43 for ; Wed, 16 Jun 2021 04:58:07 +0000 (UTC) Received: from smtpin30.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id E8335DDEC for ; Wed, 16 Jun 2021 04:58:06 +0000 (UTC) X-FDA: 78258380172.30.F3A874A Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by imf02.hostedemail.com (Postfix) with ESMTP id EC44B41AD7B6 for ; Wed, 16 Jun 2021 04:58:00 +0000 (UTC) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15G4YHf0059297; Wed, 16 Jun 2021 00:57:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=iBUHYnBQTZr8eBJ/olTHBaH0Epunv028Cq4oJo4MIp4=; b=sYSonI5Ufq6qOvXw5MiqOkfzdV5+UTOsLgzJveeecuKfs4PaN7NjzvJS0BrBzofU8iL3 yiekQ4Igeibw5mB/EMdb8lfVVrBrqwlKOxc39y63P5f3DTvH3Swc/Hihxum571nOjwVF EbskxLuDGV6zgoKyi8jrpdUpFQd3Fvkz6hsXXzJemTc/9sTapOsHZFfR0i/5Zkza5Awe uT+fJHwD1PYMf93jEgcLXbeS/iAC3NC8NEiCrXc8LhtzALmvh9k7+WfjW3LAHW/dWV4H CXc9bZ8ik1x405E8vkwNh0QU5OSRT4Ow9acQ96u+GW3784fz81TR6BcYb/20apmB8Ets +A== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 397ad18cs8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Jun 2021 00:57:55 -0400 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 15G4v9NX011714; Wed, 16 Jun 2021 00:57:55 -0400 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 397ad18cru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Jun 2021 00:57:54 -0400 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 15G4vNoJ001082; Wed, 16 Jun 2021 04:57:53 GMT Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by ppma05wdc.us.ibm.com with ESMTP id 3954gk8xp4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Jun 2021 04:57:53 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 15G4vrkd37880268 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 16 Jun 2021 04:57:53 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2A948B2066; Wed, 16 Jun 2021 04:57:53 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CADBDB2065; Wed, 16 Jun 2021 04:57:49 +0000 (GMT) Received: from skywalker.ibmuc.com (unknown [9.85.71.33]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 16 Jun 2021 04:57:49 +0000 (GMT) From: "Aneesh Kumar K.V" To: linux-mm@kvack.org, akpm@linux-foundation.org Cc: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, kaleshsingh@google.com, npiggin@gmail.com, joel@joelfernandes.org, Christophe Leroy , Linus Torvalds , "Kirill A . Shutemov" , "Aneesh Kumar K.V" Subject: [PATCH v8 2/3] powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache Date: Wed, 16 Jun 2021 10:27:34 +0530 Message-Id: <20210616045735.374532-3-aneesh.kumar@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210616045735.374532-1-aneesh.kumar@linux.ibm.com> References: <20210616045735.374532-1-aneesh.kumar@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: k9FNA7H7HV1FrR7DXt6ws08piY0k22oq X-Proofpoint-GUID: awzPzZ-ulbMuOpB_sRBFqWDSVa4dFS1J X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-06-15_09:2021-06-15,2021-06-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106160027 X-HE-Tag: 1623819480-254934 Content-Transfer-Encoding: quoted-printable X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 9C9D6F2 X-Stat-Signature: 4ni75tbt3z993h5mhyscuupe6gukr8h7 Authentication-Results: imf20.hostedemail.com; dkim=fail ("body hash did not verify") header.d=ibm.com header.s=pp1 header.b=sYSonI5U; dmarc=fail reason="No valid SPF" header.from=ibm.com (policy=none); spf=softfail (imf20.hostedemail.com: 216.40.44.93 is neither permitted nor denied by domain of aneesh.kumar@linux.ibm.com) smtp.mailfrom=aneesh.kumar@linux.ibm.com X-HE-Tag: 1623819474-197154 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: flush_tlb_range is special in that we don't specify the page size used for the translation. Hence when flushing TLB we flush the translation cac= he for all possible page sizes. The kernel also uses the same interface when moving page tables around. Such a move requires us to flush the page walk= cache. Instead of adding another interface to force page walk cache flush, update flush_tlb_range to flush page walk cache if the range flushed is more than the PMD range. A page table move will always involve an invalidate range more than PMD_SIZE. Running microbenchmark with mprotect and parallel memory access didn't show any observable performance impact. Signed-off-by: Aneesh Kumar K.V --- .../include/asm/book3s/64/tlbflush-radix.h | 2 + arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 8 +++- arch/powerpc/mm/book3s64/radix_tlb.c | 44 ++++++++++++------- 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/p= owerpc/include/asm/book3s/64/tlbflush-radix.h index 8b33601cdb9d..ab9d5e535000 100644 --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h @@ -60,6 +60,8 @@ extern void radix__flush_hugetlb_tlb_range(struct vm_ar= ea_struct *vma, unsigned long start, unsigned long end); extern void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned = long start, unsigned long end, int psize); +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned lon= g start, + unsigned long end, int psize); extern void radix__flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned = long start, diff --git a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c b/arch/powerpc/= mm/book3s64/radix_hugetlbpage.c index cb91071eef52..23d3e08911d3 100644 --- a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c +++ b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c @@ -32,7 +32,13 @@ void radix__flush_hugetlb_tlb_range(struct vm_area_str= uct *vma, unsigned long st struct hstate *hstate =3D hstate_file(vma->vm_file); =20 psize =3D hstate_get_psize(hstate); - radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize); + /* + * Flush PWC even if we get PUD_SIZE hugetlb invalidate to keep this si= mpler. + */ + if (end - start >=3D PUD_SIZE) + radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize); + else + radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize); } =20 /* diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3= s64/radix_tlb.c index 409e61210789..9f1a177f6bb6 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -989,14 +989,13 @@ static unsigned long tlb_local_single_page_flush_ce= iling __read_mostly =3D POWER9_ =20 static inline void __radix__flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) - { unsigned long pid; unsigned int page_shift =3D mmu_psize_defs[mmu_virtual_psize].shift; unsigned long page_size =3D 1UL << page_shift; unsigned long nr_pages =3D (end - start) >> page_shift; bool fullmm =3D (end =3D=3D TLB_FLUSH_ALL); - bool flush_pid; + bool flush_pid, flush_pwc =3D false; enum tlb_flush_type type; =20 pid =3D mm->context.id; @@ -1015,8 +1014,16 @@ static inline void __radix__flush_tlb_range(struct= mm_struct *mm, flush_pid =3D nr_pages > tlb_single_page_flush_ceiling; else flush_pid =3D nr_pages > tlb_local_single_page_flush_ceiling; + /* + * full pid flush already does the PWC flush. if it is not full pid + * flush check the range is more than PMD and force a pwc flush + * mremap() depends on this behaviour. + */ + if (!flush_pid && (end - start) >=3D PMD_SIZE) + flush_pwc =3D true; =20 if (!mmu_has_feature(MMU_FTR_GTSE) && type =3D=3D FLUSH_TYPE_GLOBAL) { + unsigned long type =3D H_RPTI_TYPE_TLB; unsigned long tgt =3D H_RPTI_TARGET_CMMU; unsigned long pg_sizes =3D psize_to_rpti_pgsize(mmu_virtual_psize); =20 @@ -1024,19 +1031,20 @@ static inline void __radix__flush_tlb_range(struc= t mm_struct *mm, pg_sizes |=3D psize_to_rpti_pgsize(MMU_PAGE_2M); if (atomic_read(&mm->context.copros) > 0) tgt |=3D H_RPTI_TARGET_NMMU; - pseries_rpt_invalidate(pid, tgt, H_RPTI_TYPE_TLB, pg_sizes, - start, end); + if (flush_pwc) + type |=3D H_RPTI_TYPE_PWC; + pseries_rpt_invalidate(pid, tgt, type, pg_sizes, start, end); } else if (flush_pid) { + /* + * We are now flushing a range larger than PMD size force a RIC_FLUSH_= ALL + */ if (type =3D=3D FLUSH_TYPE_LOCAL) { - _tlbiel_pid(pid, RIC_FLUSH_TLB); + _tlbiel_pid(pid, RIC_FLUSH_ALL); } else { if (cputlb_use_tlbie()) { - if (mm_needs_flush_escalation(mm)) - _tlbie_pid(pid, RIC_FLUSH_ALL); - else - _tlbie_pid(pid, RIC_FLUSH_TLB); + _tlbie_pid(pid, RIC_FLUSH_ALL); } else { - _tlbiel_pid_multicast(mm, pid, RIC_FLUSH_TLB); + _tlbiel_pid_multicast(mm, pid, RIC_FLUSH_ALL); } } } else { @@ -1052,6 +1060,9 @@ static inline void __radix__flush_tlb_range(struct = mm_struct *mm, =20 if (type =3D=3D FLUSH_TYPE_LOCAL) { asm volatile("ptesync": : :"memory"); + if (flush_pwc) + /* For PWC, only one flush is needed */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); __tlbiel_va_range(start, end, pid, page_size, mmu_virtual_psize); if (hflush) __tlbiel_va_range(hstart, hend, pid, @@ -1059,6 +1070,8 @@ static inline void __radix__flush_tlb_range(struct = mm_struct *mm, ppc_after_tlbiel_barrier(); } else if (cputlb_use_tlbie()) { asm volatile("ptesync": : :"memory"); + if (flush_pwc) + __tlbie_pid(pid, RIC_FLUSH_PWC); __tlbie_va_range(start, end, pid, page_size, mmu_virtual_psize); if (hflush) __tlbie_va_range(hstart, hend, pid, @@ -1066,10 +1079,10 @@ static inline void __radix__flush_tlb_range(struc= t mm_struct *mm, asm volatile("eieio; tlbsync; ptesync": : :"memory"); } else { _tlbiel_va_range_multicast(mm, - start, end, pid, page_size, mmu_virtual_psize, false); + start, end, pid, page_size, mmu_virtual_psize, flush_pwc); if (hflush) _tlbiel_va_range_multicast(mm, - hstart, hend, pid, PMD_SIZE, MMU_PAGE_2M, false); + hstart, hend, pid, PMD_SIZE, MMU_PAGE_2M, flush_pwc); } } out: @@ -1143,9 +1156,6 @@ void radix__flush_all_lpid_guest(unsigned int lpid) _tlbie_lpid_guest(lpid, RIC_FLUSH_ALL); } =20 -static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsig= ned long start, - unsigned long end, int psize); - void radix__tlb_flush(struct mmu_gather *tlb) { int psize =3D 0; @@ -1252,8 +1262,8 @@ void radix__flush_tlb_range_psize(struct mm_struct = *mm, unsigned long start, return __radix__flush_tlb_range_psize(mm, start, end, psize, false); } =20 -static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsig= ned long start, - unsigned long end, int psize) +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned lon= g start, + unsigned long end, int psize) { __radix__flush_tlb_range_psize(mm, start, end, psize, true); } --=20 2.31.1