* [PATCH V2]: MIPS work
@ 2021-03-05 10:03 Huang Pei
2021-03-05 10:03 ` [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table Huang Pei
2021-03-05 10:03 ` [PATCH 3/3] MIPS: loongson64: alloc pglist_data at run time Huang Pei
0 siblings, 2 replies; 5+ messages in thread
From: Huang Pei @ 2021-03-05 10:03 UTC (permalink / raw)
To: Thomas Bogendoerfer, ambrosehua
Cc: Bibo Mao, Andrew Morton, linux-mips, linux-arch, linux-mm,
Jiaxun Yang, Paul Burton, Li Xuefeng, Yang Tiezhu, Gao Juxin,
Huacai Chen, Jinyang He
PATCH 1:
No function change, just make ASE field sit close;
PATCH 2:
"CAC_BASE << 53" causes building warning MIPS32, changing CAC_BASE from
UL into ULL causes new warnings for unmatch integer size on MIP32, let's
one step back, just fix the bug, make more comment
PATCH 3:
remove space
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table
2021-03-05 10:03 [PATCH V2]: MIPS work Huang Pei
@ 2021-03-05 10:03 ` Huang Pei
2021-03-06 7:47 ` Thomas Bogendoerfer
2021-03-05 10:03 ` [PATCH 3/3] MIPS: loongson64: alloc pglist_data at run time Huang Pei
1 sibling, 1 reply; 5+ messages in thread
From: Huang Pei @ 2021-03-05 10:03 UTC (permalink / raw)
To: Thomas Bogendoerfer, ambrosehua
Cc: Bibo Mao, Andrew Morton, linux-mips, linux-arch, linux-mm,
Jiaxun Yang, Paul Burton, Li Xuefeng, Yang Tiezhu, Gao Juxin,
Huacai Chen, Jinyang He
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/include/asm/ptrace.h | 10 +++++-----
arch/mips/kernel/asm-offsets.c | 6 +++---
arch/mips/kernel/ptrace.c | 10 +++++-----
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1e76774b36dd..e51691f2b7af 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -34,16 +34,16 @@ struct pt_regs {
/* Saved main processor registers. */
unsigned long regs[32];
+ unsigned long lo;
+ unsigned long hi;
/* Saved special registers. */
+ unsigned long cp0_epc;
+ unsigned long cp0_badvaddr;
unsigned long cp0_status;
- unsigned long hi;
- unsigned long lo;
+ unsigned long cp0_cause;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
unsigned long acx;
#endif
- unsigned long cp0_badvaddr;
- unsigned long cp0_cause;
- unsigned long cp0_epc;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
unsigned long long mpl[6]; /* MTM{0-5} */
unsigned long long mtp[6]; /* MTP{0-5} */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index aebfda81120a..8a9ab78bcc63 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -60,13 +60,13 @@ void output_ptreg_defines(void)
OFFSET(PT_R31, pt_regs, regs[31]);
OFFSET(PT_LO, pt_regs, lo);
OFFSET(PT_HI, pt_regs, hi);
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
- OFFSET(PT_ACX, pt_regs, acx);
-#endif
OFFSET(PT_EPC, pt_regs, cp0_epc);
OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
OFFSET(PT_STATUS, pt_regs, cp0_status);
OFFSET(PT_CAUSE, pt_regs, cp0_cause);
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+ OFFSET(PT_ACX, pt_regs, acx);
+#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
OFFSET(PT_MPL, pt_regs, mpl);
OFFSET(PT_MTP, pt_regs, mtp);
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index db7c5be1d4a3..06ee1184fad3 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -886,15 +886,15 @@ static const struct pt_regs_offset regoffset_table[] = {
REG_OFFSET_NAME(r29, regs[29]),
REG_OFFSET_NAME(r30, regs[30]),
REG_OFFSET_NAME(r31, regs[31]),
- REG_OFFSET_NAME(c0_status, cp0_status),
- REG_OFFSET_NAME(hi, hi),
REG_OFFSET_NAME(lo, lo),
+ REG_OFFSET_NAME(hi, hi),
+ REG_OFFSET_NAME(c0_epc, cp0_epc),
+ REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
+ REG_OFFSET_NAME(c0_status, cp0_status),
+ REG_OFFSET_NAME(c0_cause, cp0_cause),
#ifdef CONFIG_CPU_HAS_SMARTMIPS
REG_OFFSET_NAME(acx, acx),
#endif
- REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
- REG_OFFSET_NAME(c0_cause, cp0_cause),
- REG_OFFSET_NAME(c0_epc, cp0_epc),
#ifdef CONFIG_CPU_CAVIUM_OCTEON
REG_OFFSET_NAME(mpl0, mpl[0]),
REG_OFFSET_NAME(mpl1, mpl[1]),
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] MIPS: loongson64: alloc pglist_data at run time
2021-03-05 10:03 [PATCH V2]: MIPS work Huang Pei
2021-03-05 10:03 ` [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table Huang Pei
@ 2021-03-05 10:03 ` Huang Pei
1 sibling, 0 replies; 5+ messages in thread
From: Huang Pei @ 2021-03-05 10:03 UTC (permalink / raw)
To: Thomas Bogendoerfer, ambrosehua
Cc: Bibo Mao, Andrew Morton, linux-mips, linux-arch, linux-mm,
Jiaxun Yang, Paul Burton, Li Xuefeng, Yang Tiezhu, Gao Juxin,
Huacai Chen, Jinyang He
It can make some metadata of MM, like pglist_data and zone
NUMA-aware
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/loongson64/numa.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
index cf9459f79f9b..afafd367cb38 100644
--- a/arch/mips/loongson64/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -26,7 +26,6 @@
#include <asm/wbflush.h>
#include <boot_param.h>
-static struct pglist_data prealloc__node_data[MAX_NUMNODES];
unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
EXPORT_SYMBOL(__node_distances);
struct pglist_data *__node_data[MAX_NUMNODES];
@@ -151,8 +150,12 @@ static void __init szmem(unsigned int node)
static void __init node_mem_init(unsigned int node)
{
+ struct pglist_data *nd;
unsigned long node_addrspace_offset;
unsigned long start_pfn, end_pfn;
+ unsigned long nd_pa;
+ int tnid;
+ const size_t nd_size = roundup(sizeof(pg_data_t), SMP_CACHE_BYTES);
node_addrspace_offset = nid_to_addrbase(node);
pr_info("Node%d's addrspace_offset is 0x%lx\n",
@@ -162,8 +165,16 @@ static void __init node_mem_init(unsigned int node)
pr_info("Node%d: start_pfn=0x%lx, end_pfn=0x%lx\n",
node, start_pfn, end_pfn);
- __node_data[node] = prealloc__node_data + node;
-
+ nd_pa = memblock_phys_alloc_try_nid(nd_size, SMP_CACHE_BYTES, node);
+ if (!nd_pa)
+ panic("Cannot allocate %zu bytes for node %d data\n",
+ nd_size, node);
+ nd = __va(nd_pa);
+ memset(nd, 0, sizeof(struct pglist_data));
+ tnid = early_pfn_to_nid(nd_pa >> PAGE_SHIFT);
+ if (tnid != node)
+ pr_info("NODE_DATA(%d) on node %d\n", node, tnid);
+ __node_data[node] = nd;
NODE_DATA(node)->node_start_pfn = start_pfn;
NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table
2021-03-05 10:03 ` [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table Huang Pei
@ 2021-03-06 7:47 ` Thomas Bogendoerfer
2021-03-07 1:36 ` 黄沛
0 siblings, 1 reply; 5+ messages in thread
From: Thomas Bogendoerfer @ 2021-03-06 7:47 UTC (permalink / raw)
To: Huang Pei
Cc: ambrosehua, Bibo Mao, Andrew Morton, linux-mips, linux-arch,
linux-mm, Jiaxun Yang, Paul Burton, Li Xuefeng, Yang Tiezhu,
Gao Juxin, Huacai Chen, Jinyang He
On Fri, Mar 05, 2021 at 06:03:08PM +0800, Huang Pei wrote:
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
> arch/mips/include/asm/ptrace.h | 10 +++++-----
> arch/mips/kernel/asm-offsets.c | 6 +++---
> arch/mips/kernel/ptrace.c | 10 +++++-----
> 3 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
> index 1e76774b36dd..e51691f2b7af 100644
> --- a/arch/mips/include/asm/ptrace.h
> +++ b/arch/mips/include/asm/ptrace.h
> @@ -34,16 +34,16 @@ struct pt_regs {
> /* Saved main processor registers. */
> unsigned long regs[32];
>
> + unsigned long lo;
> + unsigned long hi;
> /* Saved special registers. */
> + unsigned long cp0_epc;
> + unsigned long cp0_badvaddr;
> unsigned long cp0_status;
> - unsigned long hi;
> - unsigned long lo;
> + unsigned long cp0_cause;
> #ifdef CONFIG_CPU_HAS_SMARTMIPS
> unsigned long acx;
> #endif
> - unsigned long cp0_badvaddr;
> - unsigned long cp0_cause;
> - unsigned long cp0_epc;
> #ifdef CONFIG_CPU_CAVIUM_OCTEON
> unsigned long long mpl[6]; /* MTM{0-5} */
> unsigned long long mtp[6]; /* MTP{0-5} */
sorry this is pointless, I'm not taking this.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table
2021-03-06 7:47 ` Thomas Bogendoerfer
@ 2021-03-07 1:36 ` 黄沛
0 siblings, 0 replies; 5+ messages in thread
From: 黄沛 @ 2021-03-07 1:36 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: ambrosehua, Bibo Mao, Andrew Morton, linux-mips, linux-arch,
linux-mm, Jiaxun Yang, Paul Burton, Li Xuefeng, Yang Tiezhu,
Gao Juxin, Huacai Chen, Jinyang He
What about other two patches?
Current ftrace implementation is not safe on MIPS/SMP,
When disabling tracing, we need to change
Jal
Addiu sp,sp,-offset
Into
Nop
Nop
Atomically, but mips issue two writes, no
matter in what order these writes are seen by
other cpu, it is wrecked in these two case
Jal
Nop
Or,
Nop
addiu sp,sp, _offset
Huang Pei
Original Message
From: Thomas Bogendoerfer
Sent: 2021年3月6日星期六 16:06
To: Huang Pei
Cc: ambrosehua@gmail.com; Bibo Mao; Andrew Morton; linux-mips@vger.kernel.org; linux-arch@vger.kernel.org; linux-mm@kvack.org; Jiaxun Yang; Paul Burton; Li Xuefeng; Yang Tiezhu; Gao Juxin; Huacai Chen; Jinyang He
Subject: Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table
On Fri, Mar 05, 2021 at 06:03:08PM +0800, Huang Pei wrote:
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
> arch/mips/include/asm/ptrace.h | 10 +++++-----
> arch/mips/kernel/asm-offsets.c | 6 +++---
> arch/mips/kernel/ptrace.c | 10 +++++-----
> 3 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
> index 1e76774b36dd..e51691f2b7af 100644
> --- a/arch/mips/include/asm/ptrace.h
> +++ b/arch/mips/include/asm/ptrace.h
> @@ -34,16 +34,16 @@ struct pt_regs {
> /* Saved main processor registers. */
> unsigned long regs[32];
>
> + unsigned long lo;
> + unsigned long hi;
> /* Saved special registers. */
> + unsigned long cp0_epc;
> + unsigned long cp0_badvaddr;
> unsigned long cp0_status;
> - unsigned long hi;
> - unsigned long lo;
> + unsigned long cp0_cause;
> #ifdef CONFIG_CPU_HAS_SMARTMIPS
> unsigned long acx;
> #endif
> - unsigned long cp0_badvaddr;
> - unsigned long cp0_cause;
> - unsigned long cp0_epc;
> #ifdef CONFIG_CPU_CAVIUM_OCTEON
> unsigned long long mpl[6]; /* MTM{0-5} */
> unsigned long long mtp[6]; /* MTP{0-5} */
sorry this is pointless, I'm not taking this.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-03-05 10:03 [PATCH V2]: MIPS work Huang Pei
2021-03-05 10:03 ` [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table Huang Pei
2021-03-06 7:47 ` Thomas Bogendoerfer
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