From: Joerg Roedel <jroedel@suse.de>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Andi Kleen <ak@linux.intel.com>,
David Rientjes <rientjes@google.com>,
Borislav Petkov <bp@alien8.de>, Andy Lutomirski <luto@kernel.org>,
Sean Christopherson <seanjc@google.com>,
Andrew Morton <akpm@linux-foundation.org>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Jon Grimm <jon.grimm@amd.com>,
Thomas Gleixner <tglx@linutronix.de>,
Christoph Hellwig <hch@lst.de>, Ingo Molnar <mingo@redhat.com>,
x86@kernel.org, linux-mm@kvack.org
Subject: Re: AMD SEV-SNP/Intel TDX: validation of memory pages
Date: Tue, 16 Feb 2021 17:25:04 +0100 [thread overview]
Message-ID: <20210216162504.GH12716@suse.de> (raw)
In-Reply-To: <5ff9690f-331a-8322-3431-212b14f64fcc@redhat.com>
On Tue, Feb 16, 2021 at 04:59:52PM +0100, Paolo Bonzini wrote:
> - the inner handler does nothing but telling the outer handler to rerun.
> The way it does it is certainly not pretty, because it has to work at any
> instruction boundary, but at its heart it's basically a do{}while loop.
That only works if processing of all inner #VE can be deferred, which is
not the case for instruction emulation #VEs like MSR accesses, io-port
or MMIO accesses. I guess those could all be replaced direct TDCALLs,
but the question remains whether this is possible with MSR accesses, means
that the list of MSRs which will cause #VEs is statically defined and
doesn't change between hypervisors. All in all this sounds hard to
maintain and easy to break by unrelated changes.
Regards,
Joerg
next prev parent reply other threads:[~2021-02-16 16:25 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-02 1:51 David Rientjes
2021-02-02 13:17 ` Matthew Wilcox
2021-02-02 16:02 ` Kirill A. Shutemov
2021-02-03 0:16 ` Brijesh Singh
2021-02-11 17:46 ` Sean Christopherson
2021-02-02 22:37 ` Andi Kleen
2021-02-11 20:46 ` Peter Zijlstra
2021-02-12 13:19 ` Joerg Roedel
2021-02-12 14:17 ` Peter Zijlstra
2021-02-12 14:53 ` Joerg Roedel
2021-02-12 15:19 ` Peter Zijlstra
2021-02-12 15:28 ` Joerg Roedel
2021-02-12 16:12 ` Peter Zijlstra
2021-02-12 16:18 ` Joerg Roedel
2021-02-12 16:45 ` Peter Zijlstra
2021-02-12 17:48 ` Dave Hansen
2021-02-12 18:22 ` Sean Christopherson
2021-02-12 18:38 ` Andy Lutomirski
2021-02-12 18:43 ` Sean Christopherson
2021-02-12 18:46 ` Dave Hansen
2021-02-12 19:24 ` Sean Christopherson
2021-02-16 10:00 ` Joerg Roedel
2021-02-16 14:27 ` Andi Kleen
2021-02-16 14:46 ` Peter Zijlstra
2021-02-16 15:59 ` Paolo Bonzini
2021-02-16 16:25 ` Joerg Roedel [this message]
2021-02-16 16:48 ` Paolo Bonzini
2021-02-16 18:26 ` Joerg Roedel
2021-02-16 18:33 ` Paolo Bonzini
2021-02-16 16:47 ` Peter Zijlstra
2021-02-16 16:57 ` Andy Lutomirski
2021-02-16 17:05 ` Paolo Bonzini
2021-02-16 16:55 ` Andi Kleen
2021-02-12 21:42 ` Andi Kleen
2021-02-12 21:58 ` Peter Zijlstra
2021-02-12 22:39 ` Andi Kleen
2021-02-12 22:46 ` Andy Lutomirski
2021-02-13 9:38 ` Peter Zijlstra
2021-02-12 23:51 ` Paolo Bonzini
2021-03-23 9:33 ` Joerg Roedel
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