[linux-next:master 6077/10581] drivers/iommu/intel/dmar.c:1311:3: error: implicit declaration of function 'trace_qi_submit'

[linux-next:master 6077/10581] drivers/iommu/intel/dmar.c:1311:3: error: implicit declaration of function 'trace_qi_submit'

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 5003 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   671176b0016c80b3943cb5387312c886aba3308d
commit: f2dd871799ba5d80f95f9bdbc0e60d390e1bcd22 [6077/10581] iommu/vt-d: Add qi_submit trace event
config: x86_64-randconfig-a005-20210209 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
        # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=f2dd871799ba5d80f95f9bdbc0e60d390e1bcd22
        git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
        git fetch --no-tags linux-next master
        git checkout f2dd871799ba5d80f95f9bdbc0e60d390e1bcd22
        # save the attached .config to linux build tree
        make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

Note: the linux-next/master HEAD 671176b0016c80b3943cb5387312c886aba3308d builds fine.
      It may have been fixed somewhere.

All errors (new ones prefixed by >>):

   drivers/iommu/intel/dmar.c: In function 'qi_submit_sync':
>> drivers/iommu/intel/dmar.c:1311:3: error: implicit declaration of function 'trace_qi_submit' [-Werror=implicit-function-declaration]
    1311 |   trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
         |   ^~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/trace_qi_submit +1311 drivers/iommu/intel/dmar.c

  1267	
  1268	/*
  1269	 * Function to submit invalidation descriptors of all types to the queued
  1270	 * invalidation interface(QI). Multiple descriptors can be submitted at a
  1271	 * time, a wait descriptor will be appended to each submission to ensure
  1272	 * hardware has completed the invalidation before return. Wait descriptors
  1273	 * can be part of the submission but it will not be polled for completion.
  1274	 */
  1275	int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
  1276			   unsigned int count, unsigned long options)
  1277	{
  1278		struct q_inval *qi = iommu->qi;
  1279		struct qi_desc wait_desc;
  1280		int wait_index, index;
  1281		unsigned long flags;
  1282		int offset, shift;
  1283		int rc, i;
  1284	
  1285		if (!qi)
  1286			return 0;
  1287	
  1288	restart:
  1289		rc = 0;
  1290	
  1291		raw_spin_lock_irqsave(&qi->q_lock, flags);
  1292		/*
  1293		 * Check if we have enough empty slots in the queue to submit,
  1294		 * the calculation is based on:
  1295		 * # of desc + 1 wait desc + 1 space between head and tail
  1296		 */
  1297		while (qi->free_cnt < count + 2) {
  1298			raw_spin_unlock_irqrestore(&qi->q_lock, flags);
  1299			cpu_relax();
  1300			raw_spin_lock_irqsave(&qi->q_lock, flags);
  1301		}
  1302	
  1303		index = qi->free_head;
  1304		wait_index = (index + count) % QI_LENGTH;
  1305		shift = qi_shift(iommu);
  1306	
  1307		for (i = 0; i < count; i++) {
  1308			offset = ((index + i) % QI_LENGTH) << shift;
  1309			memcpy(qi->desc + offset, &desc[i], 1 << shift);
  1310			qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE;
> 1311			trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
  1312					desc[i].qw2, desc[i].qw3);
  1313		}
  1314		qi->desc_status[wait_index] = QI_IN_USE;
  1315	
  1316		wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
  1317				QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
  1318		if (options & QI_OPT_WAIT_DRAIN)
  1319			wait_desc.qw0 |= QI_IWD_PRQ_DRAIN;
  1320		wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
  1321		wait_desc.qw2 = 0;
  1322		wait_desc.qw3 = 0;
  1323	
  1324		offset = wait_index << shift;
  1325		memcpy(qi->desc + offset, &wait_desc, 1 << shift);
  1326	
  1327		qi->free_head = (qi->free_head + count + 1) % QI_LENGTH;
  1328		qi->free_cnt -= count + 1;
  1329	
  1330		/*
  1331		 * update the HW tail register indicating the presence of
  1332		 * new descriptors.
  1333		 */
  1334		writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
  1335	
  1336		while (qi->desc_status[wait_index] != QI_DONE) {
  1337			/*
  1338			 * We will leave the interrupts disabled, to prevent interrupt
  1339			 * context to queue another cmd while a cmd is already submitted
  1340			 * and waiting for completion on this cpu. This is to avoid
  1341			 * a deadlock where the interrupt context can wait indefinitely
  1342			 * for free slots in the queue.
  1343			 */
  1344			rc = qi_check_fault(iommu, index, wait_index);
  1345			if (rc)
  1346				break;
  1347	
  1348			raw_spin_unlock(&qi->q_lock);
  1349			cpu_relax();
  1350			raw_spin_lock(&qi->q_lock);
  1351		}
  1352	
  1353		for (i = 0; i < count; i++)
  1354			qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE;
  1355	
  1356		reclaim_free_desc(qi);
  1357		raw_spin_unlock_irqrestore(&qi->q_lock, flags);
  1358	
  1359		if (rc == -EAGAIN)
  1360			goto restart;
  1361	
  1362		return rc;
  1363	}
  1364	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33239 bytes --]