From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 999CDC4727E for ; Wed, 30 Sep 2020 14:10:41 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 3080920789 for ; Wed, 30 Sep 2020 14:10:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3080920789 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id B39286B0072; Wed, 30 Sep 2020 10:10:40 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id AE9476B0073; Wed, 30 Sep 2020 10:10:40 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 9FEBF6B0074; Wed, 30 Sep 2020 10:10:40 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0024.hostedemail.com [216.40.44.24]) by kanga.kvack.org (Postfix) with ESMTP id 81A9E6B0072 for ; Wed, 30 Sep 2020 10:10:40 -0400 (EDT) Received: from smtpin19.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay03.hostedemail.com (Postfix) with ESMTP id 2B9B08249980 for ; Wed, 30 Sep 2020 14:10:40 +0000 (UTC) X-FDA: 77319913440.19.air78_521364e27193 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin19.hostedemail.com (Postfix) with ESMTP id 07B411AD1B5 for ; Wed, 30 Sep 2020 14:10:40 +0000 (UTC) X-HE-Tag: air78_521364e27193 X-Filterd-Recvd-Size: 9295 Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by imf05.hostedemail.com (Postfix) with ESMTP for ; Wed, 30 Sep 2020 14:10:38 +0000 (UTC) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B3A89220FF08AE0B5235; Wed, 30 Sep 2020 22:10:30 +0800 (CST) Received: from lhrphicprd00229.huawei.com (10.123.41.22) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 22:10:23 +0800 From: Jonathan Cameron To: , , , , Lorenzo Pieralisi , , Ingo Molnar CC: Bjorn Helgaas , , Thomas Gleixner , , Dan Williams , Brice Goglin , "Sean V Kelley" , , "Borislav Petkov" , Hanjun Guo , Jonathan Cameron Subject: [PATCH v12 5/6] node: Add access1 class to represent CPU to memory characteristics Date: Wed, 30 Sep 2020 22:05:46 +0800 Message-ID: <20200930140547.840251-6-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20200930140547.840251-1-Jonathan.Cameron@huawei.com> References: <20200930140547.840251-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.123.41.22] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: New access1 class is nearly the same as access0, but always provides characteristics for CPUs to memory. The existing access0 class provides characteristics to nearest or direct connnect initiator which may be a Generic Initiator such as a GPU or network adapter. This new class allows thread placement on CPUs to be performed so as to give optimal access characteristics to memory, even if that memory is for example attached to a GPU or similar and only accessible to the CPU via an appropriate bus. Suggested-by: Dan Willaims Signed-off-by: Jonathan Cameron --- drivers/acpi/numa/hmat.c | 88 +++++++++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 19 deletions(-) diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 6a91a55229ae..3dc251264423 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -56,7 +56,7 @@ struct memory_target { unsigned int memory_pxm; unsigned int processor_pxm; struct resource memregions; - struct node_hmem_attrs hmem_attrs; + struct node_hmem_attrs hmem_attrs[2]; struct list_head caches; struct node_cache_attrs cache_attrs; bool registered; @@ -65,6 +65,7 @@ struct memory_target { struct memory_initiator { struct list_head node; unsigned int processor_pxm; + bool has_cpu; }; =20 struct memory_locality { @@ -108,6 +109,7 @@ static __init void alloc_memory_initiator(unsigned in= t cpu_pxm) return; =20 initiator->processor_pxm =3D cpu_pxm; + initiator->has_cpu =3D node_state(pxm_to_node(cpu_pxm), N_CPU); list_add_tail(&initiator->node, &initiators); } =20 @@ -215,28 +217,28 @@ static u32 hmat_normalize(u16 entry, u64 base, u8 t= ype) } =20 static void hmat_update_target_access(struct memory_target *target, - u8 type, u32 value) + u8 type, u32 value, int access) { switch (type) { case ACPI_HMAT_ACCESS_LATENCY: - target->hmem_attrs.read_latency =3D value; - target->hmem_attrs.write_latency =3D value; + target->hmem_attrs[access].read_latency =3D value; + target->hmem_attrs[access].write_latency =3D value; break; case ACPI_HMAT_READ_LATENCY: - target->hmem_attrs.read_latency =3D value; + target->hmem_attrs[access].read_latency =3D value; break; case ACPI_HMAT_WRITE_LATENCY: - target->hmem_attrs.write_latency =3D value; + target->hmem_attrs[access].write_latency =3D value; break; case ACPI_HMAT_ACCESS_BANDWIDTH: - target->hmem_attrs.read_bandwidth =3D value; - target->hmem_attrs.write_bandwidth =3D value; + target->hmem_attrs[access].read_bandwidth =3D value; + target->hmem_attrs[access].write_bandwidth =3D value; break; case ACPI_HMAT_READ_BANDWIDTH: - target->hmem_attrs.read_bandwidth =3D value; + target->hmem_attrs[access].read_bandwidth =3D value; break; case ACPI_HMAT_WRITE_BANDWIDTH: - target->hmem_attrs.write_bandwidth =3D value; + target->hmem_attrs[access].write_bandwidth =3D value; break; default: break; @@ -329,8 +331,12 @@ static __init int hmat_parse_locality(union acpi_sub= table_headers *header, =20 if (mem_hier =3D=3D ACPI_HMAT_MEMORY) { target =3D find_mem_target(targs[targ]); - if (target && target->processor_pxm =3D=3D inits[init]) - hmat_update_target_access(target, type, value); + if (target && target->processor_pxm =3D=3D inits[init]) { + hmat_update_target_access(target, type, value, 0); + /* If the node has a CPU, update access 1 */ + if (node_state(pxm_to_node(inits[init]), N_CPU)) + hmat_update_target_access(target, type, value, 1); + } } } } @@ -567,6 +573,7 @@ static void hmat_register_target_initiators(struct me= mory_target *target) unsigned int mem_nid, cpu_nid; struct memory_locality *loc =3D NULL; u32 best =3D 0; + bool access0done =3D false; int i; =20 mem_nid =3D pxm_to_node(target->memory_pxm); @@ -578,7 +585,11 @@ static void hmat_register_target_initiators(struct m= emory_target *target) if (target->processor_pxm !=3D PXM_INVAL) { cpu_nid =3D pxm_to_node(target->processor_pxm); register_memory_node_under_compute_node(mem_nid, cpu_nid, 0); - return; + access0done =3D true; + if (node_state(cpu_nid, N_CPU)) { + register_memory_node_under_compute_node(mem_nid, cpu_nid, 1); + return; + } } =20 if (list_empty(&localities)) @@ -592,6 +603,41 @@ static void hmat_register_target_initiators(struct m= emory_target *target) */ bitmap_zero(p_nodes, MAX_NUMNODES); list_sort(p_nodes, &initiators, initiator_cmp); + if (!access0done) { + for (i =3D WRITE_LATENCY; i <=3D READ_BANDWIDTH; i++) { + loc =3D localities_types[i]; + if (!loc) + continue; + + best =3D 0; + list_for_each_entry(initiator, &initiators, node) { + u32 value; + + if (!test_bit(initiator->processor_pxm, p_nodes)) + continue; + + value =3D hmat_initiator_perf(target, initiator, + loc->hmat_loc); + if (hmat_update_best(loc->hmat_loc->data_type, value, &best)) + bitmap_clear(p_nodes, 0, initiator->processor_pxm); + if (value !=3D best) + clear_bit(initiator->processor_pxm, p_nodes); + } + if (best) + hmat_update_target_access(target, loc->hmat_loc->data_type, + best, 0); + } + + for_each_set_bit(i, p_nodes, MAX_NUMNODES) { + cpu_nid =3D pxm_to_node(i); + register_memory_node_under_compute_node(mem_nid, cpu_nid, 0); + } + } + + /* Access 1 ignores Generic Initiators */ + bitmap_zero(p_nodes, MAX_NUMNODES); + list_sort(p_nodes, &initiators, initiator_cmp); + best =3D 0; for (i =3D WRITE_LATENCY; i <=3D READ_BANDWIDTH; i++) { loc =3D localities_types[i]; if (!loc) @@ -601,6 +647,10 @@ static void hmat_register_target_initiators(struct m= emory_target *target) list_for_each_entry(initiator, &initiators, node) { u32 value; =20 + if (!initiator->has_cpu) { + clear_bit(initiator->processor_pxm, p_nodes); + continue; + } if (!test_bit(initiator->processor_pxm, p_nodes)) continue; =20 @@ -611,12 +661,11 @@ static void hmat_register_target_initiators(struct = memory_target *target) clear_bit(initiator->processor_pxm, p_nodes); } if (best) - hmat_update_target_access(target, loc->hmat_loc->data_type, best); + hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1); } - for_each_set_bit(i, p_nodes, MAX_NUMNODES) { cpu_nid =3D pxm_to_node(i); - register_memory_node_under_compute_node(mem_nid, cpu_nid, 0); + register_memory_node_under_compute_node(mem_nid, cpu_nid, 1); } } =20 @@ -629,10 +678,10 @@ static void hmat_register_target_cache(struct memor= y_target *target) node_add_cache(mem_nid, &tcache->cache_attrs); } =20 -static void hmat_register_target_perf(struct memory_target *target) +static void hmat_register_target_perf(struct memory_target *target, int = access) { unsigned mem_nid =3D pxm_to_node(target->memory_pxm); - node_set_perf_attrs(mem_nid, &target->hmem_attrs, 0); + node_set_perf_attrs(mem_nid, &target->hmem_attrs[access], access); } =20 static void hmat_register_target_device(struct memory_target *target, @@ -734,7 +783,8 @@ static void hmat_register_target(struct memory_target= *target) if (!target->registered) { hmat_register_target_initiators(target); hmat_register_target_cache(target); - hmat_register_target_perf(target); + hmat_register_target_perf(target, 0); + hmat_register_target_perf(target, 1); target->registered =3D true; } mutex_unlock(&target_lock); --=20 2.19.1