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Mon, 20 Jul 2020 09:15:56 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 89F023010C8; Mon, 20 Jul 2020 11:15:54 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 7B365205A7673; Mon, 20 Jul 2020 11:15:54 +0200 (CEST) Date: Mon, 20 Jul 2020 11:15:54 +0200 From: Peter Zijlstra To: Ira Weiny Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Fenghua Yu , x86@kernel.org, Dave Hansen , Dan Williams , Vishal Verma , Andrew Morton , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH RFC V2 04/17] x86/pks: Preserve the PKRS MSR on context switch Message-ID: <20200720091554.GN10769@hirez.programming.kicks-ass.net> References: <20200717072056.73134-1-ira.weiny@intel.com> <20200717072056.73134-5-ira.weiny@intel.com> <20200717085954.GY10769@hirez.programming.kicks-ass.net> <20200717223407.GS3008823@iweiny-DESK2.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200717223407.GS3008823@iweiny-DESK2.sc.intel.com> X-Rspamd-Queue-Id: 4CA3F20358 X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam03 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Fri, Jul 17, 2020 at 03:34:07PM -0700, Ira Weiny wrote: > On Fri, Jul 17, 2020 at 10:59:54AM +0200, Peter Zijlstra wrote: > > On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.weiny@intel.com wrote: > > > +/* > > > + * Write the PKey Register Supervisor. This must be run with preemption > > > + * disabled as it does not guarantee the atomicity of updating the pkrs_cache > > > + * and MSR on its own. > > > + */ > > > +void write_pkrs(u32 pkrs_val) > > > +{ > > > + this_cpu_write(pkrs_cache, pkrs_val); > > > + wrmsrl(MSR_IA32_PKRS, pkrs_val); > > > +} > > > > Should we write that like: > > > > void write_pkrs(u32 pkr) > > { > > u32 *pkrs = get_cpu_ptr(pkrs_cache); > > if (*pkrs != pkr) { > > *pkrs = pkr; > > wrmsrl(MSR_IA32_PKRS, pkr); > > } > > put_cpu_ptrpkrs_cache); > > } > > > > given that we fundamentally need to serialize againt schedule() here. > > Yes. That seems better. > > That also means pks_sched_in() can be simplified to just > > static inline void pks_sched_in(void) > { > write_pkrs(current->thread.saved_pkrs); > } > > Because of the built WRMSR avoidance. > > However, pkrs_cache is static so I think I need to use {get,put}_cpu_var() here > don't I? Or get_cpu_ptr(&pkrs_cache), sorry for the typo :-)