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Mon, 04 May 2020 09:29:13 -0700 (PDT) Received: from myrica ([2001:171b:226e:c200:c43b:ef78:d083:b355]) by smtp.gmail.com with ESMTPSA id l5sm13656680wmi.22.2020.05.04.09.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2020 09:29:13 -0700 (PDT) Date: Mon, 4 May 2020 18:29:03 +0200 From: Jean-Philippe Brucker To: Xu Zaibo Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-mm@kvack.org, joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, felix.kuehling@amd.com, zhangfei.gao@linaro.org, jgg@ziepe.ca, fenghua.yu@intel.com, hch@infradead.org Subject: Re: [PATCH v6 01/25] mm: Add a PASID field to mm_struct Message-ID: <20200504162903.GH170104@myrica> References: <20200430143424.2787566-1-jean-philippe@linaro.org> <20200430143424.2787566-2-jean-philippe@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, May 04, 2020 at 09:52:44AM +0800, Xu Zaibo wrote: > > On 2020/4/30 22:34, Jean-Philippe Brucker wrote: > > Some devices can tag their DMA requests with a 20-bit Process Address > > Space ID (PASID), allowing them to access multiple address spaces. In > > combination with recoverable I/O page faults (for example PCIe PRI), > > PASID allows the IOMMU to share page tables with the MMU. > > > > To make sure that a single PASID is allocated for each address space, as > > required by Intel ENQCMD, store the PASID in the mm_struct. The IOMMU > > driver is in charge of serializing modifications to the PASID field. > > > > Signed-off-by: Jean-Philippe Brucker > > --- > > For the field's validity I'm thinking invalid PASID = 0. In ioasid.h we > > define INVALID_IOASID as ~0U, but I think we can now change it to 0, > > since Intel is now also reserving PASID #0 for Transactions without > > PASID and AMD IOMMU uses GIoV for this too. > > --- > > include/linux/mm_types.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h > > index 4aba6c0c2ba80..8db6472758175 100644 > > --- a/include/linux/mm_types.h > > +++ b/include/linux/mm_types.h > > @@ -534,6 +534,10 @@ struct mm_struct { > > atomic_long_t hugetlb_usage; > > #endif > > struct work_struct async_put_work; > > +#ifdef CONFIG_IOMMU_SUPPORT > > + /* Address space ID used by device DMA */ > > + unsigned int pasid; > > +#endif > Maybe '#ifdef CONFIG_IOMMU_SVA ... #endif' is more reasonable? CONFIG_IOMMU_SVA enables a few helpers but IOMMU drivers don't have to use them, so I think IOMMU_SUPPORT is more appropriate. Thanks, Jean