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Tue, 14 Apr 2020 10:04:39 -0700 (PDT) Received: from localhost.localdomain ([2001:171b:226b:54a0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id x18sm19549147wrs.11.2020.04.14.10.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 10:04:39 -0700 (PDT) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-mm@kvack.org Cc: joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, zhangfei.gao@linaro.org, jgg@ziepe.ca, xuzaibo@huawei.com, Jean-Philippe Brucker Subject: [PATCH v5 15/25] iommu/arm-smmu-v3: Enable broadcast TLB maintenance Date: Tue, 14 Apr 2020 19:02:43 +0200 Message-Id: <20200414170252.714402-16-jean-philippe@linaro.org> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200414170252.714402-1-jean-philippe@linaro.org> References: <20200414170252.714402-1-jean-philippe@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The SMMUv3 can handle invalidation targeted at TLB entries with shared ASIDs. If the implementation supports broadcast TLB maintenance, enable i= t and keep track of it in a feature bit. The SMMU will then be affected by inner-shareable TLB invalidations from other agents. A major side-effect of this change is that stage-2 translation contexts are now affected by all invalidations by VMID. VMIDs are all shared and the only ways to prevent over-invalidation, since the stage-2 page tables are not shared between CPU and SMMU, are to either disable BTM or allocat= e different VMIDs. This patch does not address the problem. Signed-off-by: Jean-Philippe Brucker --- v4->v5: bump feature bit --- drivers/iommu/arm-smmu-v3.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 21d458d817fc2..e7de8a7459fa4 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -56,6 +56,7 @@ #define IDR0_ASID16 (1 << 12) #define IDR0_ATS (1 << 10) #define IDR0_HYP (1 << 9) +#define IDR0_BTM (1 << 5) #define IDR0_COHACC (1 << 4) #define IDR0_TTF GENMASK(3, 2) #define IDR0_TTF_AARCH64 2 @@ -655,6 +656,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_VAX (1 << 14) #define ARM_SMMU_FEAT_RANGE_INV (1 << 15) #define ARM_SMMU_FEAT_E2H (1 << 16) +#define ARM_SMMU_FEAT_BTM (1 << 17) u32 features; =20 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) @@ -3814,11 +3816,14 @@ static int arm_smmu_device_reset(struct arm_smmu_= device *smmu, bool bypass) writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); =20 /* CR2 (random crap) */ - reg =3D CR2_PTM | CR2_RECINVSID; + reg =3D CR2_RECINVSID; =20 if (smmu->features & ARM_SMMU_FEAT_E2H) reg |=3D CR2_E2H; =20 + if (!(smmu->features & ARM_SMMU_FEAT_BTM)) + reg |=3D CR2_PTM; + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); =20 /* Stream table */ @@ -3929,6 +3934,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu= _device *smmu) { u32 reg; bool coherent =3D smmu->features & ARM_SMMU_FEAT_COHERENCY; + bool vhe =3D cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN); =20 /* IDR0 */ reg =3D readl_relaxed(smmu->base + ARM_SMMU_IDR0); @@ -3978,10 +3984,19 @@ static int arm_smmu_device_hw_probe(struct arm_sm= mu_device *smmu) =20 if (reg & IDR0_HYP) { smmu->features |=3D ARM_SMMU_FEAT_HYP; - if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) + if (vhe) smmu->features |=3D ARM_SMMU_FEAT_E2H; } =20 + /* + * If the CPU is using VHE, but the SMMU doesn't support it, the SMMU + * will create TLB entries for NH-EL1 world and will miss the + * broadcasted TLB invalidations that target EL2-E2H world. Don't enabl= e + * BTM in that case. + */ + if (reg & IDR0_BTM && (!vhe || reg & IDR0_HYP)) + smmu->features |=3D ARM_SMMU_FEAT_BTM; + /* * The coherency feature as set by FW is used in preference to the ID * register, but warn on mismatch. --=20 2.26.0