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[2a01:4f8:190:11c2::b:1457]) by mx.google.com with ESMTPS id e6si3103308wrq.242.2019.01.31.03.29.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Jan 2019 03:29:58 -0800 (PST) Received-SPF: pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) client-ip=2a01:4f8:190:11c2::b:1457; Authentication-Results: mx.google.com; dkim=pass header.i=@alien8.de header.s=dkim header.b=NHfrC9Gx; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=alien8.de Received: from zn.tnic (p200300EC2BCC59000D578CD19F54A2D7.dip0.t-ipconnect.de [IPv6:2003:ec:2bcc:5900:d57:8cd1:9f54:a2d7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id D60D21EC027A; Thu, 31 Jan 2019 12:29:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1548934198; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=pvDZBEHQP9vEk/hY31YWkOL84S0x4lR9x18fyrSrNy8=; b=NHfrC9Gx67nJi72GBFrjjsajVk7iywdi9/1xXraMGshYnbZwj/M+fXSJuZxh3AnaO9YLSJ PmdofcbVTIUGyqKBzoG590SOH3jmmyXkVl6AmHHrBD/62Ycau58bTvK1OAIXACqc1j0u1c urCYlYRfeLIgCEq6K6EWd3pXc+F34vs= Date: Thu, 31 Jan 2019 12:29:48 +0100 From: Borislav Petkov To: Rick Edgecombe Cc: Andy Lutomirski , Ingo Molnar , linux-kernel@vger.kernel.org, x86@kernel.org, hpa@zytor.com, Thomas Gleixner , Nadav Amit , Dave Hansen , Peter Zijlstra , linux_dti@icloud.com, linux-integrity@vger.kernel.org, linux-security-module@vger.kernel.org, akpm@linux-foundation.org, kernel-hardening@lists.openwall.com, linux-mm@kvack.org, will.deacon@arm.com, ard.biesheuvel@linaro.org, kristen@linux.intel.com, deneen.t.dock@intel.com, Kees Cook , Dave Hansen , Nadav Amit Subject: Re: [PATCH v2 03/20] x86/mm: temporary mm struct Message-ID: <20190131112948.GE6749@zn.tnic> References: <20190129003422.9328-1-rick.p.edgecombe@intel.com> <20190129003422.9328-4-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20190129003422.9328-4-rick.p.edgecombe@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: > Subject: Re: [PATCH v2 03/20] x86/mm: temporary mm struct Subject needs a verb: "Add a temporary... " On Mon, Jan 28, 2019 at 04:34:05PM -0800, Rick Edgecombe wrote: > From: Andy Lutomirski > > Sometimes we want to set a temporary page-table entries (PTEs) in one of s/a // Also, drop the "we" and make it impartial and passive: "Describe your changes in imperative mood, e.g. "make xyzzy do frotz" instead of "[This patch] makes xyzzy do frotz" or "[I] changed xyzzy to do frotz", as if you are giving orders to the codebase to change its behaviour." > the cores, without allowing other cores to use - even speculatively - > these mappings. There are two benefits for doing so: > > (1) Security: if sensitive PTEs are set, temporary mm prevents their use > in other cores. This hardens the security as it prevents exploding a exploding or exploiting? Or exposing? :) > dangling pointer to overwrite sensitive data using the sensitive PTE. > > (2) Avoiding TLB shootdowns: the PTEs do not need to be flushed in > remote page-tables. Those belong in the code comments below, explaining what it is going to be used for. > To do so a temporary mm_struct can be used. Mappings which are private > for this mm can be set in the userspace part of the address-space. > During the whole time in which the temporary mm is loaded, interrupts > must be disabled. > > The first use-case for temporary PTEs, which will follow, is for poking > the kernel text. > > [ Commit message was written by Nadav ] > > Cc: Kees Cook > Cc: Dave Hansen > Acked-by: Peter Zijlstra (Intel) > Reviewed-by: Masami Hiramatsu > Tested-by: Masami Hiramatsu > Signed-off-by: Andy Lutomirski > Signed-off-by: Nadav Amit > Signed-off-by: Rick Edgecombe > --- > arch/x86/include/asm/mmu_context.h | 32 ++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h > index 19d18fae6ec6..cd0c29e494a6 100644 > --- a/arch/x86/include/asm/mmu_context.h > +++ b/arch/x86/include/asm/mmu_context.h > @@ -356,4 +356,36 @@ static inline unsigned long __get_current_cr3_fast(void) > return cr3; > } > > +typedef struct { Why does it have to be a typedef? That prev.prev below looks unnecessary, instead of just using prev. > + struct mm_struct *prev; Why "prev"? > +} temporary_mm_state_t; That's kinda long - it is longer than the function name below. temp_mm_state_t not enough? > + > +/* > + * Using a temporary mm allows to set temporary mappings that are not accessible > + * by other cores. Such mappings are needed to perform sensitive memory writes > + * that override the kernel memory protections (e.g., W^X), without exposing the > + * temporary page-table mappings that are required for these write operations to > + * other cores. > + * > + * Context: The temporary mm needs to be used exclusively by a single core. To > + * harden security IRQs must be disabled while the temporary mm is ^ , > + * loaded, thereby preventing interrupt handler bugs from override the s/override/overriding/ > + * kernel memory protection. > + */ > +static inline temporary_mm_state_t use_temporary_mm(struct mm_struct *mm) > +{ > + temporary_mm_state_t state; > + > + lockdep_assert_irqs_disabled(); > + state.prev = this_cpu_read(cpu_tlbstate.loaded_mm); > + switch_mm_irqs_off(NULL, mm, current); > + return state; > +} > + > +static inline void unuse_temporary_mm(temporary_mm_state_t prev) > +{ > + lockdep_assert_irqs_disabled(); > + switch_mm_irqs_off(NULL, prev.prev, current); > +} > + > #endif /* _ASM_X86_MMU_CONTEXT_H */ > -- > 2.17.1 > -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.