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From: Keith Busch <keith.busch@intel.com>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-mm@kvack.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Rafael Wysocki <rafael@kernel.org>,
	Dave Hansen <dave.hansen@intel.com>,
	Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCHv3 07/13] node: Add heterogenous memory access attributes
Date: Thu, 10 Jan 2019 10:30:17 -0700	[thread overview]
Message-ID: <20190110173016.GC21095@localhost.localdomain> (raw)
In-Reply-To: <87y37sit8x.fsf@linux.ibm.com>

On Thu, Jan 10, 2019 at 06:07:02PM +0530, Aneesh Kumar K.V wrote:
> Keith Busch <keith.busch@intel.com> writes:
> 
> > Heterogeneous memory systems provide memory nodes with different latency
> > and bandwidth performance attributes. Provide a new kernel interface for
> > subsystems to register the attributes under the memory target node's
> > initiator access class. If the system provides this information, applications
> > may query these attributes when deciding which node to request memory.
> >
> > The following example shows the new sysfs hierarchy for a node exporting
> > performance attributes:
> >
> >   # tree -P "read*|write*" /sys/devices/system/node/nodeY/classZ/
> >   /sys/devices/system/node/nodeY/classZ/
> >   |-- read_bandwidth
> >   |-- read_latency
> >   |-- write_bandwidth
> >   `-- write_latency
> >
> > The bandwidth is exported as MB/s and latency is reported in nanoseconds.
> > Memory accesses from an initiator node that is not one of the memory's
> > class "Z" initiator nodes may encounter different performance than
> > reported here. When a subsystem makes use of this interface, initiators
> > of a lower class number, "Z", have better performance relative to higher
> > class numbers. When provided, class 0 is the highest performing access
> > class.
> 
> How does the definition of performance relate to bandwidth and latency here?. The
> initiator in this class has the least latency and high bandwidth? Can there
> be a scenario where both are not best for the same node? ie, for a
> target Node Y, initiator Node A gives the highest bandwidth but initiator
> Node B gets the least latency. How such a config can be represented? Or is
> that not possible?

I am not aware of a real platform that has an initiator-target pair with
better latency but worse bandwidth than any different initiator paired to
the same target. If such a thing exists and a subsystem wants to report
that, you can register any arbitrary number of groups or classes and
rank them according to how you want them presented.

  parent reply	other threads:[~2019-01-10 17:31 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-09 17:43 [PATCHv3 00/13] Heterogeneuos memory node attributes Keith Busch
2019-01-09 17:43 ` [PATCHv3 01/13] acpi: Create subtable parsing infrastructure Keith Busch
2019-01-09 17:43 ` [PATCHv3 02/13] acpi: Add HMAT to generic parsing tables Keith Busch
2019-01-10 15:36   ` Rafael J. Wysocki
2019-01-10 15:36     ` Rafael J. Wysocki
2019-01-09 17:43 ` [PATCHv3 03/13] acpi/hmat: Parse and report heterogeneous memory Keith Busch
2019-01-10 15:42   ` Rafael J. Wysocki
2019-01-10 15:42     ` Rafael J. Wysocki
2019-01-15 17:07     ` Keith Busch
2019-01-15 18:36       ` Rafael J. Wysocki
2019-01-15 18:36         ` Rafael J. Wysocki
2019-01-09 17:43 ` [PATCHv3 04/13] node: Link memory nodes to their compute nodes Keith Busch
2019-01-09 17:43 ` [PATCHv3 05/13] Documentation/ABI: Add new node sysfs attributes Keith Busch
2019-01-09 17:43 ` [PATCHv3 06/13] acpi/hmat: Register processor domain to its memory Keith Busch
2019-01-09 17:43 ` [PATCHv3 07/13] node: Add heterogenous memory access attributes Keith Busch
2019-01-10 12:37   ` Aneesh Kumar K.V
2019-01-10 12:37     ` Aneesh Kumar K.V
2019-01-10 17:30     ` Keith Busch [this message]
2019-01-11 11:32       ` Jonathan Cameron
2019-01-11 11:32         ` Jonathan Cameron
2019-01-11 15:58         ` Keith Busch
2019-01-11 16:25           ` Dan Williams
2019-01-11 16:25             ` Dan Williams
2019-01-09 17:43 ` [PATCHv3 08/13] Documentation/ABI: Add node performance attributes Keith Busch
2019-01-13 23:10   ` Pavel Machek
2019-01-14 15:53     ` Keith Busch
2019-01-09 17:43 ` [PATCHv3 09/13] acpi/hmat: Register " Keith Busch
2019-01-09 17:43 ` [PATCHv3 10/13] node: Add memory caching attributes Keith Busch
2019-01-09 17:43 ` [PATCHv3 11/13] Documentation/ABI: Add node cache attributes Keith Busch
2019-01-09 17:43 ` [PATCHv3 12/13] acpi/hmat: Register memory side " Keith Busch
2019-01-09 17:43 ` [PATCHv3 13/13] doc/mm: New documentation for memory performance Keith Busch
2019-01-13 11:42   ` Mike Rapoport
2019-01-14 15:53     ` Keith Busch

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