From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f70.google.com (mail-pg0-f70.google.com [74.125.83.70]) by kanga.kvack.org (Postfix) with ESMTP id 2FAAC6B000C for ; Wed, 21 Mar 2018 20:23:20 -0400 (EDT) Received: by mail-pg0-f70.google.com with SMTP id s6so3211694pgn.3 for ; Wed, 21 Mar 2018 17:23:20 -0700 (PDT) Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id u1-v6sor2137328pls.87.2018.03.21.17.23.19 for (Google Transport Security); Wed, 21 Mar 2018 17:23:19 -0700 (PDT) Date: Wed, 21 Mar 2018 17:23:55 -0700 From: Nicolin Chen Subject: Re: mm/hmm: a simple question regarding devm_request_mem_region() Message-ID: <20180322002352.GA12673@Asurada-Nvidia> References: <20180321222357.GA31089@Asurada-Nvidia> <20180321225632.GI3214@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180321225632.GI3214@redhat.com> Sender: owner-linux-mm@kvack.org List-ID: To: Jerome Glisse Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org On Wed, Mar 21, 2018 at 06:56:32PM -0400, Jerome Glisse wrote: > On Wed, Mar 21, 2018 at 03:23:57PM -0700, Nicolin Chen wrote: > > Hello Jerome, > > > > I started to looking at the mm/hmm code and having a question at the > > devm_request_mem_region() call in the hmm_devmem_add() implementation: > > > > > addr = min((unsigned long)iomem_resource.end, > > > (1UL << MAX_PHYSMEM_BITS) - 1); > > > > The main question is here as I am a bit confused by this addr. The code > > is trying to get an addr from the end of memory space. However, I have > > tried on an ARM64 platform where ioport_resource.end is -1, so it takes > > "(1UL << MAX_PHYSMEM_BITS) - 1" as the addr base, while this addr is way > > beyond the actual main memory size that's available on my board. Is HMM > > supposed to get an memory region like this? Would it be possible for you > > to give some hint to help me understand it? > > What are you trying to do ? hmm_devmem_add() is use either for device > private memory or device public memory. Device private memory is memory > that is not accessible by the CPU, the code you are pointing to is for > that case where i try to find a range of physical address not currently > use (memory not being accessible means that there is not any valid > physical address reserved for it). On x86 MAX_PHYSMEM_BITS is defined > to something that make sense, but as it is often the case for those > define, it seems that arm define an unreal value. My advice fix the > definition for ARM iirc it depends on the SOC dunno if you can know > that at build time. You can probably know the biggest one at build time > (1 << 47 or something like that). > > But this all assume that you have a device with its own memory that is > not accessible from the CPU. Which is very uncommon on ARM, only case > i know of is regular PCIE GPU on a ARM system with PCIE. I am testing with drivers/char/hmm_dmirror.c from your git repository. The addr I got (before "- size") is actually 0x7fffffffff, so equally (1 << 40). So from your reply, it seems to me that HMM is supposed to request a region like it. Thanks Nicolin