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From: Ingo Molnar <mingo@kernel.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	Andi Kleen <ak@linux.intel.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Andy Lutomirski <luto@amacapital.net>,
	Michal Hocko <mhocko@kernel.org>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv4 09/14] x86/mm: Handle boot-time paging mode switching at early boot
Date: Thu, 17 Aug 2017 11:10:03 +0200	[thread overview]
Message-ID: <20170817091003.qls64kolj7iec3qc@gmail.com> (raw)
In-Reply-To: <20170808125415.78842-10-kirill.shutemov@linux.intel.com>


* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:

> This patch adds detection of 5-level paging at boot-time and adjusts
> virtual memory layout and folds p4d page table layer if needed.
> 
> We have to make X86_5LEVEL dependant on SPARSEMEM_VMEMMAP.
> !SPARSEMEM_VMEMMAP configuration doesn't work well with variable
> MAX_PHYSMEM_BITS.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
>  arch/x86/Kconfig                        |  1 +
>  arch/x86/boot/compressed/kaslr.c        | 13 +++++--
>  arch/x86/entry/entry_64.S               | 12 +++++++
>  arch/x86/include/asm/page_64_types.h    | 13 +++----
>  arch/x86/include/asm/pgtable_64_types.h | 35 +++++++++++--------
>  arch/x86/include/asm/processor.h        |  2 +-
>  arch/x86/include/asm/sparsemem.h        |  9 ++---
>  arch/x86/kernel/head64.c                | 60 ++++++++++++++++++++++++++-------
>  arch/x86/kernel/head_64.S               | 18 ++++++----
>  arch/x86/kernel/setup.c                 |  5 ++-
>  arch/x86/mm/dump_pagetables.c           |  8 +++--
>  arch/x86/mm/kaslr.c                     | 13 ++++---
>  12 files changed, 129 insertions(+), 60 deletions(-)

Please also split this patch up some more, into as many individual (but 
bisectable) changes as possible.

> diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h
> index 1f5bee2c202f..ba67afd870b7 100644
> --- a/arch/x86/include/asm/sparsemem.h
> +++ b/arch/x86/include/asm/sparsemem.h
> @@ -26,13 +26,8 @@
>  # endif
>  #else /* CONFIG_X86_32 */
>  # define SECTION_SIZE_BITS	27 /* matt - 128 is convenient right now */
> -# ifdef CONFIG_X86_5LEVEL
> -#  define MAX_PHYSADDR_BITS	52
> -#  define MAX_PHYSMEM_BITS	52
> -# else
> -#  define MAX_PHYSADDR_BITS	44
> -#  define MAX_PHYSMEM_BITS	46
> -# endif
> +# define MAX_PHYSADDR_BITS	(p4d_folded ? 44 : 52)
> +# define MAX_PHYSMEM_BITS	(p4d_folded ? 46 : 52)
>  #endif

The kernel code size impact of these de-constification changes should be measured, 
double checked and documented as well. We are adding all kinds of overhead to 
(what I expect to be) commonly used kernels, let's do it carefully.

Thanks,

	Ingo

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  parent reply	other threads:[~2017-08-17  9:10 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-08 12:54 [PATCHv4 00/14] Boot-time switching between 4- and 5-level paging Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 01/14] mm/sparsemem: Allocate mem_section at runtime for SPARSEMEM_EXTREME Kirill A. Shutemov
2017-08-14 14:29   ` Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 02/14] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 03/14] x86/kasan: Use the same shadow offset for 4- and 5-level paging Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 04/14] x86/xen: Provide pre-built page tables only for XEN_PV and XEN_PVH Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 05/14] x86/xen: Drop 5-level paging support code from XEN_PV code Kirill A. Shutemov
2017-08-09 11:54   ` Juergen Gross
2017-08-08 12:54 ` [PATCHv4 06/14] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 07/14] x86/mm: Make virtual memory layout movable for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 08/14] x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable Kirill A. Shutemov
2017-08-17  9:00   ` Ingo Molnar
2017-08-17 10:54     ` Kirill A. Shutemov
2017-08-17 11:10       ` Ingo Molnar
2017-08-21 15:23         ` Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 09/14] x86/mm: Handle boot-time paging mode switching at early boot Kirill A. Shutemov
2017-08-17  9:05   ` Ingo Molnar
2017-08-17  9:10   ` Ingo Molnar [this message]
2017-08-08 12:54 ` [PATCHv4 10/14] x86/mm: Fold p4d page table layer at runtime Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 11/14] x86/mm: Replace compile-time checks for 5-level with runtime-time Kirill A. Shutemov
2017-08-17  9:17   ` Ingo Molnar
2017-08-08 12:54 ` [PATCHv4 12/14] x86/mm: Allow to boot without la57 if CONFIG_X86_5LEVEL=y Kirill A. Shutemov
2017-08-08 12:54 ` [PATCHv4 13/14] x86/xen: Allow XEN_PV and XEN_PVH to be enabled with X86_5LEVEL Kirill A. Shutemov
2017-08-09 11:50   ` Juergen Gross
2017-08-08 12:54 ` [PATCHv4 14/14] x86/mm: Offset boot-time paging mode switching cost Kirill A. Shutemov
2017-08-17  9:21   ` Ingo Molnar
2017-08-14 14:30 ` [PATCHv4 00/14] Boot-time switching between 4- and 5-level paging Kirill A. Shutemov

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