From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f200.google.com (mail-wr0-f200.google.com [209.85.128.200]) by kanga.kvack.org (Postfix) with ESMTP id 0A5936B02B4 for ; Mon, 7 Aug 2017 06:16:44 -0400 (EDT) Received: by mail-wr0-f200.google.com with SMTP id l3so14199155wrc.12 for ; Mon, 07 Aug 2017 03:16:43 -0700 (PDT) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com. [2a00:1450:400c:c09::243]) by mx.google.com with ESMTPS id j17si9696862eda.50.2017.08.07.03.16.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Aug 2017 03:16:42 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id q189so496527wmd.0 for ; Mon, 07 Aug 2017 03:16:42 -0700 (PDT) Date: Mon, 7 Aug 2017 13:16:39 +0300 From: "Kirill A. Shutemov" Subject: Re: [PATCH -mm] mm: Clear to access sub-page last when clearing huge page Message-ID: <20170807101639.4fb4v42jynkscep6@node.shutemov.name> References: <20170807072131.8343-1-ying.huang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170807072131.8343-1-ying.huang@intel.com> Sender: owner-linux-mm@kvack.org List-ID: To: "Huang, Ying" Cc: Andrew Morton , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrea Arcangeli , "Kirill A. Shutemov" , Nadia Yvette Chambers , Michal Hocko , Jan Kara , Matthew Wilcox , Hugh Dickins , Minchan Kim , Shaohua Li On Mon, Aug 07, 2017 at 03:21:31PM +0800, Huang, Ying wrote: > From: Huang Ying > > Huge page helps to reduce TLB miss rate, but it has higher cache > footprint, sometimes this may cause some issue. For example, when > clearing huge page on x86_64 platform, the cache footprint is 2M. But > on a Xeon E5 v3 2699 CPU, there are 18 cores, 36 threads, and only 45M > LLC (last level cache). That is, in average, there are 2.5M LLC for > each core and 1.25M LLC for each thread. If the cache pressure is > heavy when clearing the huge page, and we clear the huge page from the > begin to the end, it is possible that the begin of huge page is > evicted from the cache after we finishing clearing the end of the huge > page. And it is possible for the application to access the begin of > the huge page after clearing the huge page. > > To help the above situation, in this patch, when we clear a huge page, > the order to clear sub-pages is changed. In quite some situation, we > can get the address that the application will access after we clear > the huge page, for example, in a page fault handler. Instead of > clearing the huge page from begin to end, we will clear the sub-pages > farthest from the the sub-page to access firstly, and clear the > sub-page to access last. This will make the sub-page to access most > cache-hot and sub-pages around it more cache-hot too. If we cannot > know the address the application will access, the begin of the huge > page is assumed to be the the address the application will access. > > With this patch, the throughput increases ~28.3% in vm-scalability > anon-w-seq test case with 72 processes on a 2 socket Xeon E5 v3 2699 > system (36 cores, 72 threads). The test case creates 72 processes, > each process mmap a big anonymous memory area and writes to it from > the begin to the end. For each process, other processes could be seen > as other workload which generates heavy cache pressure. At the same > time, the cache miss rate reduced from ~33.4% to ~31.7%, the > IPC (instruction per cycle) increased from 0.56 to 0.74, and the time > spent in user space is reduced ~7.9% That's impressive. But what about the case when we are not bounded that much by the size of LLC? What about running the same test on the same hardware, but with 4 processes instead of 72. I just want to make sure we don't regress on more realistic tast case. -- Kirill A. Shutemov -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org