From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
Dan Williams <dan.j.williams@intel.com>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCHv5, REBASED 1/9] x86/asm: Fix comment in return_from_SYSCALL_64
Date: Mon, 15 May 2017 15:12:10 +0300 [thread overview]
Message-ID: <20170515121218.27610-2-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20170515121218.27610-1-kirill.shutemov@linux.intel.com>
On x86-64 __VIRTUAL_MASK_SHIFT depends on paging mode now.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
arch/x86/entry/entry_64.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 607d72c4a485..edec30584eb8 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -266,7 +266,8 @@ return_from_SYSCALL_64:
* If width of "canonical tail" ever becomes variable, this will need
* to be updated to remain correct on both old and new CPUs.
*
- * Change top 16 bits to be the sign-extension of 47th bit
+ * Change top bits to match most significant bit (47th or 56th bit
+ * depending on paging mode) in the address.
*/
shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
--
2.11.0
--
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next prev parent reply other threads:[~2017-05-15 12:12 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-15 12:12 [PATCHv5, REBASED 0/9] x86: 5-level paging enabling for v4.12, Part 4 Kirill A. Shutemov
2017-05-15 12:12 ` Kirill A. Shutemov [this message]
2017-05-15 12:12 ` [PATCHv5, REBASED 2/9] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 3/9] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 4/9] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 5/9] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 6/9] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 7/9] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov
2017-05-15 12:12 ` [PATCHv5, REBASED 8/9] x86: Enable 5-level paging support Kirill A. Shutemov
2017-05-15 12:31 ` Juergen Gross
2017-05-15 14:11 ` Kirill A. Shutemov
2017-05-15 14:13 ` Juergen Gross
2017-05-15 12:12 ` [PATCHv5, REBASED 9/9] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov
2017-05-15 14:49 ` kbuild test robot
2017-05-15 19:48 ` Kirill A. Shutemov
2017-05-18 11:43 ` Michal Hocko
2017-05-18 15:19 ` Kirill A. Shutemov
2017-05-18 15:27 ` Michal Hocko
2017-05-18 15:41 ` Kirill A. Shutemov
2017-05-18 15:50 ` Michal Hocko
2017-05-18 15:59 ` Michal Hocko
2017-05-18 16:22 ` Kirill A. Shutemov
2017-05-18 17:13 ` Michal Hocko
2017-05-18 17:51 ` Michal Hocko
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