Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

[Henrique de Moraes Holschuh <hmh@hmh.eng.br>]

On Thu, 04 Sep 2014, Toshi Kani wrote:
> This patch sets WT to the PA4 slot in the PAT MSR when the processor
> is not affected by the PAT errata.  The upper 4 slots of the PAT MSR
> are continued to be unused on the following Intel processors.
> 
>   errata           cpuid
>   --------------------------------------
>   Pentium 2, A52   family 0x6, model 0x5
>   Pentium 3, E27   family 0x6, model 0x7
>   Pentium M, Y26   family 0x6, model 0x9
>   Pentium 4, N46   family 0xf, model 0x0
> 
> For these affected processors, _PAGE_CACHE_MODE_WT is redirected to UC-
> per the default setup in __cachemode2pte_tbl[].

There are at least two PAT errata.  The blacklist is in
arch/x86/kernel/cpu/intel.c:

        if (c->x86 == 6 && c->x86_model < 15)
                clear_cpu_cap(c, X86_FEATURE_PAT);

It covers model 13, which is not in your blacklist.

It *is* possible that PAT would work on model 13, as I don't think it has
any PAT errata listed and it was blacklisted "just in case" (from memory. I
did not re-check), but this is untested, and unwise to enable on an aging
platform.

I am worried of uncharted territory, here.  I'd actually advocate for not
enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP
is using them as well.  Is this a real concern, or am I being overly
cautious?

-- 
  "One disk to rule them all, One disk to find them. One disk to bring
  them all and in the darkness grind them. In the Land of Redmond
  where the shadows lie." -- The Silicon Valley Tarot
  Henrique Holschuh

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