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([2600:1700:2000:b002:1d3e:176c:909c:5aed]) by smtp.gmail.com with ESMTPSA id x1-20020a0ce241000000b0065d89f4d537sm1516928qvl.45.2023.10.04.11.49.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Oct 2023 11:49:58 -0700 (PDT) Message-ID: <20075b03-e3b0-4f29-9ba1-98eed361a44f@sifive.com> Date: Wed, 4 Oct 2023 13:49:56 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards Content-Language: en-US To: "Lad, Prabhakar" , Robin Murphy Cc: Ulf Hansson , Jisheng Zhang , Drew Fustini , linux-kernel@vger.kernel.org, Linux-MM , Guo Ren , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Christoph Hellwig , Geert Uytterhoeven , Fabrizio Castro , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , Alexandre Ghiti , Arnd Bergmann , Han Gao , Lad Prabhakar , Jason Kridner , Paul Walmsley , Robert Nelson , linux-mmc@vger.kernel.org, Adrian Hunter , Conor Dooley , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Rob Herring , Palmer Dabbelt , Xi Ruoyao , Fu Wei References: <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com> From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 5778610001B X-Rspam-User: X-Stat-Signature: fttsgbz77hwiwps93m9brtrab1jctbh9 X-Rspamd-Server: rspam03 X-HE-Tag: 1696445400-537516 X-HE-Meta: U2FsdGVkX1+s1Sfq7/oxg7BYL1eBZOr87qHnNbe51SwQC3ojmOGWyQdIFQ9WxWRBNiJvHJgzLxBVSavTY8afJq3ivABsHvrcWw+cP1Yw0iWLjmXRi5jAt/tHkzkKQowJhGff4nw14+5HLnFshcre4ovrpjLZTSteiGiAyQuX9MEEU7GznohA2w1lPaIW4fgXlOxd0erYME4I0GuQznz61lCDBJp6cKkV2dTiDr/MWTg8YjEuCeoUrTuz/K18n2pX0jEv/kcFAaR0r2jB2SZTYRCYTZDDjqXhBdfCo09dJuFlZmVzDyzLp5SFdRCB5tUFp3ZfI9Zo85u/SbgctcOte9FkOaVbR2pwycZK6QuEfYcWPt0HAsocYvpB6AMuIWox2jEb858giGkMOjatV+kXDjipRNl2MDSlgS6/6uOz6X9dnQd2QXmMuLXB8KNPj56aDbn7PbIOly8oX8KiUHPWPsVWCl4W5H+OhAfvHc2DJ7v0PSp/4BtpFkRI5k0+nTxkRHCL3Aon6A8WwxhFznI/S+xCxbcgHrfWZFBZYJkskW4NlphvY2XtsWg6fDq8ovy2Z47d2lOfDJMo6Wd34ppmfvnNz81udwdgymVJH3lAhMOrFpAJaF3unsihvDBhmneJpdEpowduUVMv7AetOlxoNIZc9UGMgPqbkk4sSms41ahN7R5RaCJ3lxFdV9jwFajkgh4fd7obAEDhGKombkk8P0HWSVWpJCAmjJguxiTroqM6vSVOpbbtET1whQj0o5gV/J+XCQ/GmWqIZxIHz4GNzkJQe8a5421AUk8NyFQC5eKdNEq45wXk4tycxxTlGIpW1Tl/PudzsEgHKKnpDV4Rvw/GEMgzjgATjDMg/w1fhOkI1rIvXIIoB8PFZ+s6/ThFjU8Vg6zKyMMcfHOhPPj6m9pYGVZYT8T019QteT+UP298i7f1ByOIUSPdYpUbhWoAgr252r3lSEm34gvKVL5 1Lk7jzaA k9m6+pKXGzNP/Fucqc50fz9RwuftnbswpzKF6U7rh3sWQF2zSFshBtYEX1L+uPsEyOjqGRSD2XO5vOBzag/OY0gjj2JnHSa6FM1BF7PCKzAu0oO3IKpmskh1GvwEIFVyf2V4s5LZ54iS9TwhiMWYymWktG1I5jZ2MMdZPWGXzIAo20iPhhoxbajPUwAaHr4toMsXBNRRgjNwil4+6I3rlkpW+i790nnZ1PwTzKOX1Cgv3T9kOgjeIuWgI0xOK1scHY2cQRswUKR517Ifs+oNhe7IkqnFDBlez6Liyi7GqTaFmF5sEaGMazCX0rpURZmSqlTsRcHTruzjGhUQnmqP4S4+3XhmZNNyTndVkziFzduQln4kuyeI+ofeHwpxW5AnB5Y1T/kdi9s3iMncq3YjDlFNc1v6V1rq0J9Wj53iSCxyXsgk4aYCSrP/HxSvjRRDqaiI/ZiLAqz1cZ6Vnjs3KZOrZiZ6GyN8dh32rRX2L2teKcSkAImwd0EGJ7fh+5Rh+X+MpSM2uaJRPFg/6drccTYHxI2DXMp+1Q5QN2rP26+oUt8J8h+lM6i4ncA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 2023-10-04 12:16 PM, Lad, Prabhakar wrote: > On Wed, Oct 4, 2023 at 5:03 PM Lad, Prabhakar > wrote: >> >> On Wed, Oct 4, 2023 at 3:18 PM Robin Murphy wrote: >>> >>> On 04/10/2023 3:02 pm, Icenowy Zheng wrote: >>> [...] >>>>>>> I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select the >>>>>>> required configs for RZ/Five SoC") can cause regression on all >>>>>>> non-dma-coherent riscv platforms with generic defconfig. This is >>>>>>> a common issue. The logic here is: generic riscv defconfig >>>>>>> selects >>>>>>> ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all >>>>>>> non-dma-coherent riscv platforms have a dma global pool, this >>>>>>> assumption >>>>>>> seems not correct. And I believe DMA_GLOBAL_POOL should not be >>>>>>> selected by ARCH_SOCFAMILIY, instead, only ARCH under some >>>>>>> specific >>>>>>> conditions can select it globaly, for example NOMMU ARM and so >>>>>>> on. >>>>>>> >>>>>>> Since this is a regression, what's proper fix? any suggestion is >>>>>>> appreciated. >>>>> >>>>> I think the answer is to not select DMA_GLOBAL_POOL, since that is >>>>> only >>>> >>>> Well I think for RISC-V, it's not NOMMU only but applicable for every >>>> core that does not support Svpbmt or vendor-specific alternatives, >>>> because the original RISC-V priv spec does not define memory attributes >>>> in page table entries. >>>> >>>> For the Renesas/Andes case I think a pool is set by OpenSBI with >>>> vendor-specific M-mode facility and then passed in DT, and the S-mode >>>> (which MMU is enabled in) just sees fixed memory attributes, in this >>>> case I think DMA_GLOBAL_POOL is needed. >>> >>> Oh wow, is that really a thing? In that case, either you just can't >>> support this platform in a multi-platform kernel, or someone needs to do >>> some fiddly work in dma-direct to a) introduce the notion of an optional >>> global pool, >> Looking at the code [0] we do have compile time check for >> CONFIG_DMA_GLOBAL_POOL irrespective of this being present in DT or >> not, instead if we make it compile time and runtime check ie either >> check for DT node or see if pool is available and only then proceed >> for allocation form this pool. >> >> What are your thoughts on this? >> > Something like the below: > > diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h > index f2fc203fb8a1..7bf41a4634a4 100644 > --- a/include/linux/dma-map-ops.h > +++ b/include/linux/dma-map-ops.h > @@ -198,6 +198,7 @@ int dma_release_from_global_coherent(int order, > void *vaddr); > int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr, > size_t size, int *ret); > int dma_init_global_coherent(phys_addr_t phys_addr, size_t size); > +bool dma_global_pool_available(void); > #else > static inline void *dma_alloc_from_global_coherent(struct device *dev, > ssize_t size, dma_addr_t *dma_handle) > @@ -213,6 +214,10 @@ static inline int > dma_mmap_from_global_coherent(struct vm_area_struct *vma, > { > return 0; > } > +static inline bool dma_global_pool_available(void) > +{ > + return false; > +} > #endif /* CONFIG_DMA_GLOBAL_POOL */ > > /* > diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c > index c21abc77c53e..605f243b8262 100644 > --- a/kernel/dma/coherent.c > +++ b/kernel/dma/coherent.c > @@ -277,6 +277,14 @@ int dma_mmap_from_dev_coherent(struct device > *dev, struct vm_area_struct *vma, > #ifdef CONFIG_DMA_GLOBAL_POOL > static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_init; > > +bool dma_global_pool_available(void) > +{ > + if (!dma_coherent_default_memory) > + return false; > + > + return true; > +} > + > void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size, > dma_addr_t *dma_handle) > { > diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c > index 9596ae1aa0da..a599bb731ceb 100644 > --- a/kernel/dma/direct.c > +++ b/kernel/dma/direct.c > @@ -235,7 +235,7 @@ void *dma_direct_alloc(struct device *dev, size_t size, > * If there is a global pool, always allocate from it for > * non-coherent devices. > */ > - if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL)) > + if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) && > dma_global_pool_available()) > return dma_alloc_from_global_coherent(dev, size, > dma_handle); dma_alloc_from_global_coherent() already checks dma_coherent_default_memory, so the solution could be even simpler: --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -232,12 +232,12 @@ void *dma_direct_alloc(struct device *dev, size_t size, attrs); /* - * If there is a global pool, always allocate from it for + * If there is a global pool, always try to allocate from it for * non-coherent devices. */ - if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL)) - return dma_alloc_from_global_coherent(dev, size, - dma_handle); + ret = dma_alloc_from_global_coherent(dev, size, dma_handle); + if (ret) + return ret; /* * Otherwise remap if the architecture is asking for it. But Regards, Samuel