From: John Fusco <fusco_john@yahoo.com>
To: Andi Kleen <ak@suse.de>
Cc: linux-mm@kvack.org
Subject: Re: Making PCI Memory Cachable
Date: Sat, 9 Dec 2006 06:33:41 -0800 (PST) [thread overview]
Message-ID: <20061209143341.90545.qmail@web52308.mail.yahoo.com> (raw)
----- Original Message ----
From: Andi Kleen <ak@suse.de>
To: John Fusco <fusco_john@yahoo.com>
Cc: linux-mm@kvack.org
Sent: Wednesday, December 6, 2006 4:16:27 PM
Subject: Re: Making PCI Memory Cachable
On Tuesday 28 November 2006 15:02, John Fusco wrote:
> I have numerous custom PCI devices that implement SRAM or DRAM on the
> PCI bus. I would like to explore making this memory cachable in the
> hopes that writes to memory can be done from user space and will be done
> in bursts rather than single cycles.
You want write combining, not cacheable. The only way to do
this currently is to set a MTRR. See Documentation/mtrr.txt
by default.
> b) The memory is cachable, but the chipset is throttling the bursts
The normal cache coherency protocol doesn't work over PCI
-Andi
Thanks for the reply.
I am aware of the MTRRs, but I was hoping for a more elegant solution.
BTW, why won't cache coherency protocol work over PCI? It has commands to support this, such as "memory read line" and "memory write line". Is it that Linux does not allow memory outside of RAM to be cacheable?
John
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next reply other threads:[~2006-12-09 14:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-12-09 14:33 John Fusco [this message]
2006-12-09 21:36 ` Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2006-11-28 14:02 John Fusco
2006-12-06 22:16 ` Andi Kleen
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