From: Andi Kleen <ak@suse.de>
To: John Fusco <fusco_john@yahoo.com>
Cc: linux-mm@kvack.org
Subject: Re: Making PCI Memory Cachable
Date: Wed, 6 Dec 2006 23:16:27 +0100 [thread overview]
Message-ID: <200612062316.27898.ak@suse.de> (raw)
In-Reply-To: <456C4182.4020302@yahoo.com>
On Tuesday 28 November 2006 15:02, John Fusco wrote:
> I have numerous custom PCI devices that implement SRAM or DRAM on the
> PCI bus. I would like to explore making this memory cachable in the
> hopes that writes to memory can be done from user space and will be done
> in bursts rather than single cycles.
You want write combining, not cacheable. The only way to do
this currently is to set a MTRR. See Documentation/mtrr.txt
by default.
> b) The memory is cachable, but the chipset is throttling the bursts
The normal cache coherency protocol doesn't work over PCI
-Andi
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next prev parent reply other threads:[~2006-12-06 22:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-28 14:02 John Fusco
2006-12-06 22:16 ` Andi Kleen [this message]
2006-12-09 14:33 John Fusco
2006-12-09 21:36 ` Andi Kleen
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