Re: sparsemem & sparsemem extreme question

[Bob Picco <bob.picco@hp.com>]

Heiko Carstens wrote:	[Wed Oct 05 2005, 02:04:43PM EDT]
> > > > > Anything specific you need to know about the memory layout?
> > > > How sparse is it?  How few present pages can be there be in a worst-case
> > > > physical area?
> > > 
> > > Worst case that is already currently valid is that you can have 1 MB
> > > segments whereever you want in address space.
> > ...
> > > Even though it's currently not possible to define memory segments above
> > > 1TB, this limit is likely to go away.
> > 
> > Go away, or get moved up?
> > 
> > ia64 today is designed to work with 50 bits of physical address space,
> > and 30 bit sections.  That's exactly the same scale that you're talking
> > about with 1MB sections and 1TB of physical space.  So, sparsemem
> > extreme should be perfectly fine for that case (that's explicitly what
> > it was designed for).
> > 
> > How much bigger than 1TB will it go?
> 
> As already mentioned, we will have physical memory with the MSB set. Afaik
> the hardware uses this bit to distinguish between different types of memory.
> So we are going to have the full 64 bit address space.
> 
> Heiko
Possibly the architects did a similar thing to ia64.  When bit 63 is set the
access in uncached. This doesn't seem relevant to sparsemem.  The attribute
could be stored in page structure flags or some other way.

bob

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